Showing papers on "Automatic test pattern generation published in 1995"

An experimental chip to evaluate test techniques experiment results

Abstract: This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for CrossCheck, Very-Low-Voltage, IDDQ and delay tests are also given.

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

Abstract: This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M

Method for manufacturing test simulation in electronic circuit design

Abstract: A manufacturing and test simulation method for electronic circuit design integrated with computer aided design tools to provide concurrent engineering of manufacturing and testability aspects of a product concurrent with the functional design of a product. The manufacturing and test simulator (MTSIM) simulates manufacturing test and repair aspects of boards and multichip modules (MCMs) from design concept through manufacturing release to aid the designer in selecting appropriate trade-offs in the design for manufacturability and the design for testability. All simulation by the methods of the present invention applies manufacturing and test models down to the component level. The methods of the simulator include a new yield model for boards and MCMs which accounts for the clustering of solder defects. MTSIM models solder faults, manufacturing workmanship faults, component performance faults, and reliability faults. Fault probabilities for the circuit design are estimated based on the component type, the component functionality, and the assembly process used. Up to seven manufacturing test steps can be simulated by MTSIM. Test coverage models will support all commonly used manufacturing test methodologies, including visual inspection, in-circuit test, IEEE 1149.1 boundary scan, selftest, diagnostics, and burn-in. Pareto and iterative "what-if" analysis may be used to locate particular enhancements which most benefit the manufacturability and testability of the product.

Pattern generation for a deterministic BIST scheme

Abstract: Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced hardware overhead compared to encoding a conventionally generated test set.

Combinational and sequential logic optimization by redundancy addition and removal

Abstract: This paper presents a method for multilevel logic optimization for combinational and synchronous sequential circuits. The circuits are optimized through iterative addition and removal of redundancies. Adding redundant wires to a circuit may cause one or many existing irredundant wires and/or gates to become redundant. If the amount of added redundancies is less than the amount of created redundancies, the transformation of adding followed by removing redundancies will result in a smaller circuit. Based upon the Automatic Test Pattern Generation (ATPG) techniques, the proposed method can efficiently identify those wires for addition that would create more redundancies elsewhere in the network. Experiments on ISCAS-85 combinational benchmark circuits show that best results are obtained for most of them. For sequential circuits, experimental results on MCNC FSM benchmarks and ISCAS-89 sequential benchmark circuits show that a significant amount of area reduction can be achieved beyond combinational optimization and sequential redundancy removal. >

Test set compaction for combinational circuits

Abstract: Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage. The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS'85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST. >

Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST

Abstract: During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new technique for synthesizing combinational mapping logic to transform the set of patterns that are generated. The goal is to satisfy test length and fault coverage requirements while minimizing area overhead. For a given pseudo-random pattern generator and circuit under test, there are many possible mapping functions that will provide a desired fault coverage for a given test length. This paper formulates the problem of finding a mapping function that can be implemented with a small number of gates as a one of finding a minimum rectangle cover in a binate matrix. A procedure is described for selecting a mapping function and synthesizing mapping logic to implement it. Experimental results for the procedure are compared with published results for other methods. It is shown that by performing iterative global operations, the procedure described in this paper generates mapping logic that requires less hardware overhead to achieve the same fault coverage for the same test length.

Multifrequency analysis of faults in analog circuits

Abstract: Testability analysis of analog circuits in the presence of soft, large-deviation, and hard faults greatly facilitates production of testable systems. The authors analyze these faults by observing their symptoms at the circuit's output, an approach that uses the same test methodology to analyze all three fault types. Their algorithm indicates the set of adequate test frequencies and nodes that increase fault observability. They conclude by generating test vectors for observing and covering these faults. >

Test application time reduction for sequential circuits with scan

Abstract: Scan designs alleviate the test generation problem for sequential circuits. However, scan operations substantially increase the total number of test clocks during test application stage. Classical methods used to solve this problem perform test compaction and obtain fewer test vectors. In this paper we show that such a strategy does not always reduce the test clocks or test application time. Our approach is to associate a scan strategy function with each test vector during test generation for circuits with full or partial scan. The paper presents two algorithms to generate test sequences that reduce the number of test clocks required to apply the test sequences. The algorithms are based on: (1) heuristics that determine the need for scan operations; and (2) controlling sequential test generation process by choosing an appropriate target fault. In this paper we define and investigate different scan strategies for full and partial scan designs. We propose approximate measures that can be used for selection of a target fault during sequential test generation. These concepts are integrated into the algorithms Test Application time Reduction for Full scan (TARF) and Test Application time Reduction for Partial scan (TARP). The algorithms are implemented, and their efficiencies are demonstrated by using them for a set of ISCAS sequential benchmark circuits. The experiments show that, in full scan designs, TARF generated vectors require 36% fewer test clocks compared to the vectors from COMPACTEST that produces near optimal test sets. Similarly for partial scan designs, TARP achieves over 30% cumulative test clock reduction compared to the results from FASTEST which produced generally fewer vectors than other ATPG systems. >

Combinational ATPG theorems for identifying untestable faults in sequential circuits

Abstract: We give two theorems for identifying untestable faults in sequential circuits. The first, the single-fault theorem, states that if a single fault in a combinational array is untestable then that fault is untestable in the sequential circuit. The array replicates the combinational logic and can have any finite length. We assume that the present state inputs of the left-most block are completely controllable. The next state outputs of the right-most block are considered observable. A combinational test pattern generator determines the detectability of single faults in the right-most block. The second theorem, called the multifault theorem, uses the array model with a multifault consisting of a single fault in every block. The theorem states that an untestable multifault in the array corresponds to an untestable single fault in the sequential circuit. For the array with a single block both theorems identify combinational redundancies. Experiments on ISCAS benchmarks show that using a small array size (typically, two to four blocks) we can identify a large number of sequentially untestable faults. >

Classification and test generation for path-delay faults using single stuck-fault tests

Abstract: In this paper, we classify path-delay faults into three categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent (ST-dependent). All ST faults are guaranteed detection in the case of a single fault, and some may be guaranteed detection through robust and validatable non-robust tests even in the case of multiple faults. An ST-dependent fault can affect the circuit speed only if certain ST faults are present. Thus, if the ST faults are tested, the ST-dependent faults need not be tested. MT faults cannot be guaranteed detection, but affect the speed only if delay faults simultaneously exist on a set of paths none of which is ST. We classify all path-delay faults into the three categories by a procedure using any unaltered single stuck fault test generation tool. We use only two runs of this tool on a network derived from the original network. As a by-product of this process, we generate single and multiple input change delay tests for all testable faults. With these tests, we expect that most defective circuits are identified. Examples and results on ISCAS'89 benchmarks are presented.

Transformed pseudo-random patterns for BIST

Abstract: This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. The transformation is performed by a small amount of mapping logic that decodes sets of patterns that don't detect any new faults and maps them into patterns that detect the hard-to-detect faults. The mapping logic is purely combinational and is placed between the pseudo-random pattern generator and the circuit under test (CUT). A procedure for designing the mapping logic so that it satisfies test length and fault coverage requirements is described. Results are shown for benchmark circuits which indicate that an LFSR plus a small amount of mapping logic reduces the test length required for a particular fault coverage by orders of magnitude compared with using an LFSR alone. These results are compared with previously published results for other methods, and it is shown that the proposed method requires much less overhead to achieve the same fault coverage for the same test length.

Test generation for path delay faults using binary decision diagrams

Abstract: A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust-hazard-free-test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS '89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms. >

Complexity of sequential ATPG

Abstract: The research reported in this paper was conducted to identify those attributes, of both sequential circuits and structural, sequential automatic test pattern generation (ATPG) algorithms, which can lead to extremely high test generation times. The retiming transformation is used as a mechanism to create two classes of circuits which present varying degrees of complexity for test generation. It was observed for three different sequential test generators that the increase in complexity of testing is not due to those circuit attributes (namely sequential depth and cycles) which have traditionally been associated with such complexity. Evidence is instead provided that another circuit attribute, termed density of encoding, is a key indicator of the complexity of structural, sequential ATPG. >

A controller for implementing scan testing

Abstract: A test access port controller is provided for implementing scan testing with a chain of scan latches on an integrated circuit. The test access port controller can implement a structural test or a performance test. Selection between the two types of test is achieved through logic circuitry of the test access port controller. An integrated circuit and a test system are also provided.

Finding defects with fault models

Abstract: A process is presented to validate fault models used in fault diagnosis. Known defects are inserted, using a focused ion beam (FIB), into production ICs and their behavior is compared to that predicted in fault simulation. The fault model is refined until it matches the observed defect behavior. The process is then repeated with known defects in unknown ("blind") locations, and necessary modifications to the model are again made. Finally, the model is used to diagnose chips with unknown defects. Experimental results on several chips demonstrate the value of the approach, which can be extended to test pattern generation and test quality estimation as well as fault diagnosis.

Delay fault coverage, test set size, and performance trade-offs

Abstract: The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, this implies very large test sets for most circuits. Not surprisingly, all known analysis and synthesis techniques for 100% path delay fault testability are computationally infeasible on large circuits. We prove that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it. These are termed robust dependent delay faults and need not be considered in delay fault testing. Necessary and sufficient conditions under which a set of path delay faults is robust dependent are proved; this yields more accurate and increased delay fault coverage estimates than previously used. Next, assuming only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed (clock period) can be selected such that 100% robust delay fault coverage is achieved. This leads to a quantitative tradeoff between the testing effort (measured by the size of the test set) for a circuit and the verifiability of its performance. Finally, under a bounded delay model, we show that the test set size can be reduced while maintaining the delay fault coverage for the specified circuit speed. Examples and experimental results are given to show the effect of these three techniques on the amount of delay fault testing necessary to guarantee correct operation. >

Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation

Abstract: A hybrid sequential circuit test generator is described which combines deterministic algorithms for fault excitation and propagation with genetic algorithms for state justification. Deterministic procedures for state justification are used if the genetic approach is unsuccessful, to allow for identification of untestable faults and to improve the fault coverage. High fault coverages were obtained for the ISCAS89 benchmark circuits and several additional circuits, and in many cases the results are better than those for purely deterministic approaches.

A methodology to design efficient BIST test pattern generators

Abstract: This paper describes a new technique to design efficient test pattern generators (TPGs) for built-in self-test (BIST). The proposed technique identifies compatible circuit inputs that can be connected to the same TPG stage in the test mode. Compatibility between circuit inputs is determined by analyzing the circuit function to guarantee coverage of all faults in a given target fault set. Unlike pseudo-exhaustive testing, circuit inputs that fanout to the same output can be compatible, provided that connecting them to the same TPG stage does not cause any loss of fault coverage. Experimental results show that TPGs designed by the proposed technique achieve 100% stuck-at fault coverage in practical test length (/spl les/2/sup 28/) with low hardware overhead and performance penalty for a wide range of benchmark circuits.

A deterministic built-in self-test generator based on cellular automata structures

Abstract: This paper proposes a new approach for designing a cost-effective, on-chip, deterministic, built-in, self-test generator. Given a set of precomputed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector generator (TVG) is synthesized to apply the given test set in a minimal test time. To achieve this objective, cellular automata (CA) structures have been used in which the rule space is not limited to the linear rules commonly used in CA studies recently. Based on some new notations and new formulations of CA properties, two techniques are developed to synthesize such a TVG which is used to generate an ordered/unordered deterministic test vector set. The resulting TVG is very efficient in terms of hardware size and speed performance, and is very regular and testable. Simulation of various benchmark combinational circuits has given good results when compared to alternative solutions. >

Test synthesis in the behavioral domain

Abstract: A method for test synthesis in the behavioral domain is described. The approach is based on the addition of test behavior, which is the behavior of the design in test mode. The normal-mode design behavior and test-mode test behavior are combined and synthesized together to produce a testable design with inserted BIST structures. Derivation of an appropriate test behavior uses analysis based on metrics that quantify the testability of signals embedded within behaviors. The synthesized circuit is tested using a behavioral test scheme which allows the test controller to be easily embedded within the system controller, and the entire datapath and controller to be easily tested together. Results show that when the testability insertion procedure is used to modify a behavior before synthesis, the resulting synthesized physical implementation is indeed more easily tested than an implementation synthesized directly from the original behavior.

A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level

Abstract: The properties of Gate Oxide Short defects (GOS) in CMOS circuits are investigated identifying the most relevant parameters that determine the behavior of a defective device Electrical models of the defect are developed and compared with experimentation Depending upon location and transistor type, GOSs are resistive, diode, parasitic MOSFET or parasitic BJT We also investigate the necessary conditions to detect a GOS at the circuit level, providing the bases for an efficient ATPG approach

Defect isolation using scan-path testing and electron beam probing in multi-level high density asics

Abstract: A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit's modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).

On generating compact test sequences for synchronous sequential circuits

Abstract: We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test application time and memory requirements. The proposed procedure constructs a test sequence using a combination of fault-independent and fault-oriented criteria. Experimental results are presented to demonstrate its effectiveness.

Qualitative model-based fault detection in air-handling units

Abstract: The feasibility of a qualitative approach for detecting faults in an air-conditioning system is considered. The system considered is a multi-zone variable air volume air-handling unit, and the faults investigated include types which result in deterioration of operation, as distinct from actual failure. The operating modes of the sequential controller for the central air-handling plant can be matched to a corresponding qualitative classification of steady-state temperatures. Observed mismatches indicate the presence of faults. Trials of the method in an air-conditioning test laboratory are reported. >

A parallel algorithm for fault simulation based on PROOFS

Abstract: Fault simulation for sequential circuits numbers among the highly compute intensive tasks in the integrated circuit design process. In the quest for rapid design turn around, parallelization has been proposed to speed fault simulation. We introduce ProperPROOFS, a parallel extension of the PROOFS fault simulation package. ProperPROOFS exploits parallelism based on fault partitioning, incorporating static and dynamic partitioning schemes and a new asynchronous and distributed method of fault redistribution. We present results for circuits in the ISCAS-89 benchmark set across several parallel architectures. A detailed evaluation of results provides new insight into the use of fault partitioning to parallelize high performance serial fault simulation applications.

Design based analog testing by Characteristic Observation Inference

Abstract: In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is prohibitive to directly verify the circuit specifications due to the test equipment costs. Our approach considers a given universal set of reasonable input stimuli and measurements that can be performed with the given test equipment. From this universal set, a minimal number of measurements is automatically selected that represent a set of observations characterizing the state of the circuit under test with respect to parametric faults. A parametric fault model is introduced which is related to the individual circuit specifications. For each given circuit specification, a corresponding test inference criterion is computed, based on logistic discrimination analysis. By applying these criteria, the satisfaction or violation of the given circuit specifications can be inferred from the observations of the circuit under test. The COI method applied to a complex operational amplifier yields very encouraging simulated results with respect to parametric faults as well as to catastrophic faults.

Method and apparatus for a universal programmable boundary scan driver/sensor circuit

Abstract: A circuit and technique is described for adding boundary scan test capability to circuit boards and systems, thereby improving the ability to test and verify proper operation of such systems using nonintrusive methods. An integrated circuit consisting of a serial path of input/output buffers, an instruction register, and a serial test access port circuit is described. The integrated circuit can be coupled to a number of input and output signals, and the serial test bus is then used in conjunction with the test access port and instruction register circuitry to observe or control any or all of the signals present at the pins of the integrated circuit. Each pin may be programmed as an input or output for a particular operation. Because the integrated circuit is programmable and can be applied to any system, the need for design of special test hardware is eliminated, and the user may build in boundary scan capability into any arbitrary system. This is of particular importance when adding test capability to systems comprised of an array of off-the-shelf components, many of which do not have these capabilities.

GARDA: a diagnostic ATPG for large synchronous sequential circuits

Abstract: The paper deals with automated generation of diagnostic test sequences for synchronous sequential circuits. An algorithm is proposed, named GARDA, which is suitable to produce good results with acceptable CPU time and memory requirements even for the largest benchmark circuits. The algorithm is based on Genetic Algorithms, and experimental results are provided which demonstrate the effectiveness of the approach. >

A realistic defect oriented testability methodology for analog circuits

Abstract: Owing to the non-binary nature of their operation, analog circuits are influenced by process defects in a different manner compared to digital circuits. This calls for a careful investigation into the occurrence of defects in analog circuits, their modeling related aspects and their detection strategies. In this article, we demonstrate with the help of a real CMOS circuit that simple test stimuli, like DC, transient and AC, can detect most of the modeled process defects. Silicon devices tested with the proposed test methodology demonstrate the effectiveness of the method. Subsequently, the proposed test method is implemented in production test environment along with the conventional test for a comparative study. This test methodology is structured and simpler, therefore results in substantial test cost reduction.