Showing papers on "Automatic test pattern generation published in 1997"

Equivalence checking using cuts and heaps

Abstract: This paper presents a verification technique which isspecifically targeted to formally comparing large combinational circuits with some structural similarities. The approach combines the application of BDDs withcircuit graph hashing, automatic insertion of multiple cut frontiers, and a controlled elimination of false negative verification results caused by the cuts. Twoideas fundamentally distinguish the presented technique from previous approaches. First, originating from the cut frontiers, multiple BDDs are computedfor the internal nets of the circuit, and second, theBDD propagation is prioritized by size and discontinued once a given limit is exceeded.

Sequential circuit test generation using dynamic state traversal

Abstract: This research was supported in part by the Semiconductor Research Corporation under contract SRC 96-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques.

Linear circuit fault diagnosis using neuromorphic analyzers

Abstract: This paper presents a method of analog fault diagnosis using neural networks. The primary focus of the paper is to provide robust diagnosis using a simple mechanism for automatic test pattern generation while reducing test time. A new diagnosis framework consisting of a white noise generator and an artificial neural network for response analysis and classification is proposed. This approach moves the diagnosis of analog circuits closer to the goal of built-in test. Networks of reasonable dimension are shown to be capable of robust diagnosis of analog circuits including effects due to tolerances.

Testing analog and mixed-signal integrated circuits using oscillation-test method

Abstract: A new low-cost test method for analog integrated circuits, called the oscillation test, is presented. During the test mode, the circuit under test (CUT) is converted to a circuit that oscillates. Faults in the CUT which deviate the oscillation frequency from its tolerance band can be detected. Using this test method, no test vector is required to be applied. Therefore, the test vector generation problem is eliminated, and the test time is very small because only a single output frequency is evaluated for each CUT. The oscillation frequency may be considered as a digital signal and therefore can be evaluated using pure digital circuitry. These characteristics imply that the oscillation-test strategy is very attractive for wafer-probe testing as well as final production testing. In this note, the validity of the proposed test method has been verified throughout various examples such as operational amplifiers, amplifiers, filters, and analog-to-digital converters (ADCs). The simulations and practical implementation results affirm that the presented method assures a high fault coverage.

A low overhead design for testability and test generation technique for core-based systems

Abstract: In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagating test responses from the core outputs. In this paper, we present a design for testability and symbolic test generation technique for testing such core-based systems on a chip. The proposed method consists of two parts: (i) core-level DFT to make each core testable and transparent, the latter needed to propagate test data through the cores, and (ii) system-level DFT and test generation to ensure the justification and propagation of the precomputed test sequences and test responses of the core. Since the hierarchical testability analysis technique used to tackle the above problem is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a by-product of the testability analysis and insertion method without further search. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated on two example systems: (i) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan, and (ii) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

Test of RAM-based FPGA: methodology and application to the interconnect

Abstract: This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.

Test set size minimization and fault detection effectiveness: a case study in a space application

Abstract: An important question in software testing is whether it is reasonable to apply coverage based criteria as a filter to reduce the size of a test set. An empirical study was conducted using a test set minimization technique to explore the effect of reducing the size of a test set, while keeping block coverage constant, on the fault detection strength of the resulting minimized test set. Two types of test sets were examined. For those with respect to a fixed size, no test case screening was conducted during the generation, whereas for those with respect to a fixed coverage, each subsequent test case had to improve the overall coverage in order to be included. The study reveals that no matter how a test set is generated (with or without any test case screening) block minimized test sets have a size/effectiveness advantage, in terms of a significant reduction in test set size but with almost the same fault detection effectiveness, over the original non-minimized test sets.

Robust search algorithms for test pattern generation

Abstract: In recent years several highly effective algorithms have been proposed for Automatic Test Pattern Generation (ATPG). Nevertheless, most of these algorithms too often rely on different types of heuristics to achieve good empirical performance. Moreover there has not been significant research work on developing algorithms that are robust, in the sense that they can handle most faults with little heuristic guidance. In this paper we describe an algorithm for ATPG that is robust and still very efficient. In contrast with existing algorithms for ATPG, the proposed algorithm reduces heuristic knowledge to a minimum and relies on an optimized search algorithm for effectively pruning the search space. Even though the experimental results are obtained using an ATPG tool built on top of a Propositional Satisfiability (SAT) algorithm, the same concepts can be integrated on application-specific algorithms.

Testing embedded cores using partial isolation rings

Abstract: Intellectual property cores pose a significant test challenge. The core supplier may not give any information about the internal logic of the core, but simply provide a set of test vectors for the core which guarantees a particular fault coverage. If the core is embedded within a larger design, then the problem is how to apply the specified test vectors to the core and how to test the user-defined logic around the core. A simple and fast solution is to place a full isolation ring (i.e., boundary scan) around the core, however, the area and performance overhead for this may not be acceptable in many applications. This paper presents a systematic method for designing a partial isolation ring that provides the same fault coverage as a full isolation ring, but avoids adding MUXes on critical timing paths and reduces area overhead. Efficient ATPG techniques are used to analyze the user-defined logic surrounding the core and identify a maximal set of core inputs and outputs (that includes the critical timing paths) that do not need to be included in the partial isolation ring. Several different partial isolation ring selection strategies that vary in computational complexity are described. Experimental results are shown comparing the different strategies.

An operational test device and method of performing an operational test for a system under test

Abstract: The invention relates to an operational test device and a method of executing an operational test for a test system which can assume a number of operating states. A test case generator (TCG) is provided for generating a number of test cases which are sent via a test device interface (INT) to the system under test (SUT). A test state model of the test system is ascertained by a test state model generator (TSTM-G) from information on the hardware configuration of the test system (SUT), information on the possible operating states of the test system (SUT), information on the test commands necessary for bringing about changes in operating state within the test system (SUT), and from traffic values which indicate transitional probabilities ascertained in the test system's real application for the operating states. Test commands are generated on the basis of the Monte-Carlo simulation of this test state model. The operational test device is particularly suitable for use with a Petri net state model for testing a telephone network or in particular a mobile telephone network such as a GSM network, e.g. for interrupting connection lines therein.

Method and apparatus for pattern recognition of wafer test bins

Abstract: An automated system and procedure processes wafer test bin data of semiconductor wafers to formulate a fault pattern at statistically significant levels. A processor such as a neural engine or neural network collects wafer test bin results to generate a N/N wafer map to be correlated with wafer maps produced from a wafer electrical test, a wafer level reliability test, and an in-line defect analysis. A N/N wafer map generated by the processor is cross-checked with a wafer map generated from another semiconductor tester to formulate possible overlap fault patterns. The confirmed fault patterns are further analyzed by performing failure analysis to find the root cause of fault patterns. A report containing fault patterns and the root cause for fault patterns is sent back to a fab for making adjustment to the fabrication process to increase the overall yield of the future batch of semiconductor wafers. The report is also stored in a pattern database to serve as a library for future reference of previously recognized fault patterns, thereby to bypass the need to perform a failure analysis for matching fault patterns.

Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques

Abstract: Foreword. Preface. 1. Preliminaries. 2. Combinational ATPG. 3. Recursive Learning. 3. And/Or Reasoning Graphs. 5. Logic Optimization. 6. Logic Verification. 7. Conclusions and Future Work. References. Appendix. Index.

A genetic algorithm framework for test generation

Abstract: Test generation using deterministic fault-oriented algorithms is highly complex and time consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. Genetic algorithms (GA's) have been effective in solving many search and optimization problems. Since test generation is a search process over a large vector space, it is an ideal candidate for GA's. In this work, we describe a GA framework for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including alphabet size, fitness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the ISCAS'89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases.

ATPG for heat dissipation minimization during scan testing

Abstract: An ATPG technique is proposed that reduces heat dissipationduring testing of sequential circuits that have full-scan. The objectiveis to permit safe and inexpensive testing of low power circuitsand bare die that would otherwise require expensive heat removalequipment for testing at high speeds. The proposed ATPG exploitsall don't cares that occur during scan shifting, test application, andresponse capture to minimize switching activity in the circuit undertest. Furthermore, an ATPG that maximizes the number of state inputsthat are assigned don't care values, has been developed. Theproposedtechniquehas beenimplemented and usedto generatetestsfor full scan versions of ISCAS 89 benchmark circuits. These testsdecrease the average number of transitions during test by 19% to89%, when comparedwith those generatedby a simple PODEM implementation.

Compact test sets for high defect coverage

Abstract: It was recently observed that, in order to improve the defect coverage of a test set, test generation based on fault models such as the single-line stuck-at model may need to be augmented so as to derive test sets that detect each modeled fault more than once. In this work, we report on test pattern generators for combinational circuits that generate test sets to detect each single line stuck-at fault a given number of times. Additionally, we study the effects of test set compaction on the defect coverage of such test sets. For the purpose of experimentation, defect coverage is measured by the coverage of surrogate faults, using a framework proposed earlier. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction if the test set is computed using appropriate test generation objectives. Moreover, two test sets generated using the same test generation objectives, except that compaction heuristics were used during the generation of one but not the other, typically have similar defect coverages, even if the compacted test set is significantly smaller than the noncompacted one. Test generation procedures and experimental results to support these claims are presented.

A novel functional test generation method for processors using commercial ATPG

Abstract: As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper describes a novel method for hierarchical functional test generation for processors which targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Applying the technique to benchmark processor designs, we were able to obtain test efficiencies for the embedded modules of the processors which were extremely close to what the commercial ATPG could do with complete access to the module. The hierarchical approach used produced this result, using the same commercial tool, but required a CPU time several orders of magnitude less than when using a conventional, flat view of the circuit.

Test case design based on Z and the classification-tree method

Abstract: Software testing often consumes up to 50 percent of the overall software costs. A large amount of time and money within the test process is spent due to incomplete, inconsistent or ambiguous informal specifications of the test objects. A more formal approach to the early phases of software development can reduce the error rate drastically and in addition, can significantly improve the central testing activities like test case design and test evaluation. This paper presents an approach for generating test cases from formal specifications written in Z by combining the classification-tree method for partition testing with the disjunctive normal form approach. Firstly, a classification tree describing high level test cases is constructed from the formal specification of the test object. Then the high level test cases are further refined by generating a disjunctive normal form for them. The refined test cases obtained this way cover all specified aspects of the system explicitly and also contain all information necessary to evaluate the test results. The proposed combination of the classification-tree method with the disjunctive normal form approach preserves advantages of both methods, overcomes most of their limitations, and can be supported by tools.

Testability analysis and ATPG on behavioral RT-level VHDL

Abstract: This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient.

An efficient method for compressing test data

Abstract: The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. A compression algorithm for test data should meet two requirements: lossless and simple decompression. In this paper we propose a new test data compression method that aims to fully utilize the unique characteristics of test data compression. The key idea of the proposed method is to perform the Burrows-Wheeler transformation on the sequence of test patterns, and then to apply run-length coding. The experimental results show that our compression method performs better than six other methods for compressing test data. The average compression ratio of the proposed method performed on five test data sets is 315, while that for the next best one, the LZW method, is 21.

An optimized BIST test pattern generator for delay testing

Abstract: As delay testing using external testers requires expensive equipment, built-in self-test (BIST) is an alternative technique that can significantly reduce the test cost. In this paper, a BIST test pattern generator (TPG) design for the detection of delay faults is proposed. This TPG design produces test sequences having exactly the same robust delay fault coverage as single input change (SIC) test sequences obtained with the most efficient TPGs proposed before in the literature, but with a reduced test length and less area overhead. This reduction of the test length and area overhead is obtained by determining compatible inputs of the circuit under test (CUT), i.e. inputs that can be switch simultaneously without altering the robust test coverage.

Vector generation for maximum instantaneous current through supply lines for CMOS circuits

Abstract: We present two new algorithms for generating a smallset of patterns for estimating the maximum instantaneouscurrent through the power supply lines for CMOScircuits.The first algorithm is based on timed ATPG,while the second is a probability-based approach.Bothalgorithms can handle circuits with arbitrary but knowndelays and they produce a set of 2-vector tests.Experimentalresults demonstrating that the outcome of applyingour algorithms is a small set of patterns producinga current that is a tight lower bound on the maximuminstantaneous current are included.

Digital circuit testing and testability

Abstract: Faults in Digital Circuits: Failures and Faults. Modeling of Faults. Temporary Faults. Test Generation for Combinational Logic Circuits: Fault Diagnosis of Digital Circuits. Test Generation Techniques for Combinatorial Circuits. Multiple Fault Detection in Combinational Logic Circuits. Testable Combinational Logic Circuit Design: The Reed-Muller Expansion Technique. Three Level OR-AND-OR Design. Automatic Synthesis of Testable Logic. Testable Design of Multi-Level Combinational Circuits. Synthesis of Random Pattern Testable Combinational Circuits. Path Delay Fault Testable Combinational Logic Design. Testable PLA Design. Test Generation for Sequential Circuits: Testing of Sequential Circuits as IterativeCombinational Circuits. State Table Verification. Test Generation Based on Circuit Structure. Functional Fault Models. Test Generation Based on Functional Fault Models. Design of Testable Sequential Circuits: Controllability and Observability. Ad hoc Design Rules for Improving Testability. Design of Diagnosable Sequential Circuits. The Scan-Path Technique for Testable Sequential Circuit Design. Level-Sensitive Scan Design (LSSD). Random Access Scan Technique. Partial Scan. Testable Sequential Circuit Design Using Non-Scan Techniques. Cross Check. Boundary Scan. Built-In Self Test: Test Pattern for BIST. Output Response Analysis. Circular BIST. BIST Architecture. Testable Memory Design: RAM Fault Models. Test Algorithms for RAMs. Detection of Pattern Sensitive Faults. BIST Techniques for RAM Chips. Test Generation and BIST for Embedded RAMs. Subject Index.

Properties of the input pattern fault model

Abstract: Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists

Abstract: The paper presents a flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits. Evaluation and derivation of implications are essential in ATPG, equivalence checking, and netlist optimization. Contrary to other methods, the approach is based on a graph model of a circuit's clause description called implication graph. It combines both the flexibility of SAT-based techniques and high efficiency of structure based methods. As the proposed algorithms operate only on the implication graph, they are independent of the chosen logic. Evaluation of implications and computation of indirect implications are performed by simple and efficient graph algorithms. Experimental results for various applications relying on implication demonstrate the effectiveness of the approach.

Built-in self-test methodology for A/D converters

Abstract: A (partial) Built-in Self-Test (BIST) methodology is proposed for analog to digital (A/D) converters. In this methodology the number of bits of the A/D converter that needs to be monitored externally in a test is reduced. This reduction depends, among other things, on the frequency of the applied test signal. At low test signal frequencies only the least significant bit (LSB) needs to be monitored and a "full" BIST becomes feasible. An analysis is made of the trade-off between the size of the on-chip test circuitry and the accuracy of this BIST technique.

Fast identification of untestable delay faults using implications

Abstract: We propose a novel algorithm to rapidly identify untestable delay faults using pre-computed static logic implications. Our fault-independent analysis identifies large sets of untestable faults, if any, without enumerating them. The cardinalities of these sets are obtained by using a counting algorithm that has quadratic complexity in the number of lines. Since our method is based on an incomplete set of logic implications, it gives only a lower bound of the number of untestable faults. A post-processing step can list the untestable faults, if desired. Targeting untestable delay faults for test generation by an automatic test pattern generation (ATPG) tool can be avoided. The method works on the segment delay fault model and its special case, the path delay fault model, to identify robustly untestable, non-robustly untestable, and functionally unsensitizable delay faults. Results on benchmark circuits show that many delay faults are identified as untestable in a very short time. For the benchmark circuit c6288, our algorithm identified 1.978 x 10^20 functionally unsensitizable path faults in 3 CPU seconds.

Logic optimization and equivalence checking by implication analysis

Abstract: This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuck-at faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effective heuristics are presented to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are "good" candidates for the minimization of the circuit. A main advantage of the proposed approach is that it operates directly on the structural netlist description of the circuit so that the technical consequences of the performed transformations can be evaluated in an easy way, permitting better control of the optimization process with respect to the specific goals of the designer. Therefore, the presented technique can serve as a basis for optimization techniques targeting nonconventional design goals. This paper only considers area minimization, and our experimental results show that the method presented is competitive with conventional technology-independent minimization techniques. For many benchmark circuits, our tool, the Hannover implication tool, based on learning (HANNIBAL) achieves the best minimization results published to date. Furthermore, the optimization approach presented is shown to be useful in formal verification.

Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis

Abstract: In this paper we discuss the capabilities of the MiST PROFIT (Mixed Signal Test Program for Fault Insertion and Testing) software for hierarchical fault modeling, tolerance modeling, fault clustering and fault diagnosis of complex mixed-signal systems. The software is designed to exploit the relationships between high level system specifications and module-level faults in complex and nonlinear mixed signal systems. Hierarchical simulation based methods are used to capture fault effects at different levels of circuit abstraction. The key features of our approach are: (a) the ability to compute tolerance effects from nonlinear behavioral models at different levels of circuit design hierarchy accurately using low-cost simulation based methods, (b) the ability to perform compaction of fault effects while transferring fault effects from the leaf cells to the highest level behavioral models, (c) the ability to capture parametric (soft) failure effects over the entire anticipated range of faulty parameter values and (d) the ability to construct fault dictionaries given a set of least replaceable units to diagnose.

HABIST: histogram-based analog built in self test

Abstract: This histogram based method of test collects a statistical representation of the activity at a node and processes that representation using a template histogram as a reference. In most cases, no special stimulus is required-data is collected in-situ, while the circuit under test is functioning. (Alternatively, analog stimulus, e.g. using a pseudo random sequence generator or stored digital vectors with a D to A converter, may be provided). The result of processing the data against the template histogram is a compressed human readable signature that defines gain, offset, noise, and distortion errors. These errors can then be used heuristically to determine causation. This paper describes the HABIST method and optional variations in its implementation, algorithms for processing histograms to obtain signatures and other compressed form of data, including waveform parameters, examples of the difference histograms that result from applying the algorithm, and methods and circuits for histogram generation.

Fast algorithms for static compaction of sequential circuit test vectors

Abstract: Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and sufficient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states.