Showing papers on "Automatic test pattern generation published in 1998"

Test set compaction algorithms for combinational circuits

Abstract: This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating the minimum single stuck at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits.

Techniques for minimizing power dissipation in scan and combinational circuits during test application

Abstract: Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.

Test vector decompression via cyclical scan chains and its application to testing core-based designs

Abstract: A novel test vector compression/decompression technique is proposed for reducing the amount of test data that must be stored on a tester and transferred to each core when testing a core-based design. A small amount of on-chip circuitry is used to reduce both the test storage and test time required for testing a core-based design. The fully specified test vectors provided by the core vendor are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the core (the compression is lossless). Instead of having to transfer each entire test vector from the tester to the core, a smaller amount of compressed data is transferred instead. This reduces the amount of test data that must be stored on the tester and hence reduces the total amount of test time required for transferring the data with a given test data bandwidth.

A structured test re-use methodology for core-based system chips

Abstract: This paper describes a structured test re-use methodology and infrastructure for core-based system chips. The methodology is based on the use of a structured test bus framework that provides access to virtual components in a system chip allowing the test methodologies and test vectors for these components to be re-used. It addresses the test access, isolation, interconnect and shadow logic test problems without requiring modifications to the components, even for cores with more ports than chip pins. The test area overhead required, including test bus routing, to implement this methodology can be less than 1%.

Scan chain design for test time reduction in core-based ICs

Abstract: The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test application time and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector set for a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pins to embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number of scan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-based ICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC. Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varying design parameters.

Effect of test set minimization on fault detection effectiveness

Abstract: Given a test set T to test a program P, there are at least two attributes of T that determine its fault detection effectiveness. One attribute is the size of T measured as the number of test cases in T. Another attribute is the code coverage measured when P is executed on all elements of T. The fault detection effectiveness of T is the ratio of the number of faults guaranteed to result in program failure when P is executed on T to the total number of faults present in P. An empirical study was conducted to determine the relative importance of the size and coverage attributes in affecting the fault detection effectiveness of a randomly selected test set for some program P. Results from this study indicate that as the size of a test set is reduced, while the code coverage is kept constant, there is little or no reduction in the fault detection effectiveness of the new test set so generated. For the study reported, of the two attributes mentioned above, the code coverage attribute of a test set is more important than its size attribute. © 1998 John Wiley & Sons, Ltd.

Using a single input to support multiple scan chains

Abstract: Single scan chain architectures suffer from long test application time, while multiple scan chain architectures require large pin overhead and are not supported by boundary scan. We present a novel method to allow a single input line to support multiple scan chains. By appropriately connecting the inputs of all circuits under test during ATPG process such that the generated test patterns can be broadcast to all scan chains when actual testing is executed, we show that 177 and 280 test patterns are enough to detect all detectable faults in all 10 ISCAS'85 combinational circuits and 10 largest ISCAS'89 sequential circuits, respectively.

Testing the interconnect of RAM-based FPGAs

Abstract: Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

ATPG for heat dissipation minimization during test application

Abstract: A automatic test pattern generator (ATPG) algorithm is proposed that reduces switching activity (between successive test vectors) during test application. The main objective is to permit safe and inexpensive testing of low power circuits and bare die that might otherwise require expensive heat removal equipment for testing at high speeds, Three new cost functions, namely transition controllability, observability, and test generation costs, have been defined. It has been shown, for a fanout free circuit under test, that the transition test generation cost for a fault is the minimum number of transitions required to test a given stuck-at fault. The proposed algorithm has been implemented and the generated tests are compared with those generated by a standard PODEM implementation for the larger ISCAS85 benchmark circuits. The results clearly demonstrate that the tests generated using the proposed ATPG can decrease the average number of (weighted) transitions between successive test vectors by a factor of 2 to 23.

Test generation in VLSI circuits for crosstalk noise

Abstract: This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These effects are becoming more prevalent due to short signal switching times and deep submicron circuitry. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We first present a new way for predicting the output waveform produced by an inverter due to a non-square wave pulse at its input. Our modeling technique captures such properties as the amplitude of a pulse and its rise/fall times and the delay through a device. To expedite the computation of the response of a logic gate to an input pulse, we have developed a novel way of modeling such gates by an equivalent inverter. We have developed a mixed-signal test generator that incorporates classical PODEM-like static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. We also present a new analog cost function that is used to guide the search process. Comparison of results with SPICE simulations confirms the accuracy of this approach. This paper focuses primarily on crosstalk induced pulses, but these results have been extended to deal with speedup and slowdown effects.

Test data decompression for multiple scan designs with boundary scan

Abstract: The paper presents an efficient scheme to compress and decompress in parallel deterministic test patterns for circuits with multiple scan chains. It employs a boundary-scan-based environment for high quality testing with flexible trade-offs between test data volume and test application time while achieving a complete fault coverage for any fault model for which test cubes are obtainable. It also reduces bandwidth requirements, as all test cube transfers involve compressed data. The test patterns are generated by the reseeding of a two-dimensional hardware structure which is comprised of a linear feedback shift register (LFSR), a network of exclusive-or (XOR) gates used to scramble the bits of test vectors, and extra feedbacks which allow including internal scan flip-flops into the decompressor structure to minimize the area overhead. The test data decompressor operates in two modes: pseudorandom and deterministic. In the first mode, the pseudorandom pattern generator (PRPG) is used purely as a generator of test vectors. In the latter case, variable-length seeds are serially scanned through the boundary-scan interface into the PRPG and parts of internal scan chains and, subsequently, a decompression is performed in parallel by means of the PRPG and selected scan flip-flops interconnected to form the decompression device. Extensive experiments with the largest ISCAS' 89 benchmarks show that the proposed technique greatly reduces the amount of test data in a cost effective manner.

Abstraction techniques for validation coverage analysis and test generation

Abstract: The enormous state spaces which must be searched when verifying the correctness of, or generating tests for, complex circuits precludes the use of traditional approaches. Hard-to-find abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. This control flow, capturing the essential "behavior" of the circuit, is represented as a finite state machine called the ECFM (Extracted Control Flow Machine). Simulation is currently the primary means of verifying large circuits, but the definition of a coverage measure for simulation vectors is an open problem. We define functional coverage as the amount of control behavior covered by the test suite. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph. We also demonstrate how the same abstraction techniques can complement ATPG techniques when attacking hard-to-detect faults in the control part of the design for which conventional ATPG alone proves to be inadequate or inefficient at best. Results on large designs show significant improvement over conventional algorithms.

Reducing power consumption during test application by test vector ordering

Abstract: This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on a re-ordering of the vectors in the test sequence to minimize the switching activity of the circuit during test application. Our technique uses the Hamming distance between test vectors and guarantees a decrease in power consumption and heat dissipation without modifying the initial fault coverage. Results of experiments are presented at the end of this paper and shows a reduction of the circuit activity in the range from 8.2 to 54.1% during test application.

Method for verification of combinational circuits using a filtering oriented approach

Abstract: A set of filters are arranged in sequence for verification and analysis of digital circuit designs. The filters are either active filters, which are directly involved in verification of circuit designs (e.g., a Binary Decision Diagram (BDD)-based verifier or an automatic test pattern generation (ATPG)-based verifier), or passive filters, which gather information about the circuit or transform the circuit structure in order to simplify the verification problem (e.g., random pattern simulation or circuit partitioning). Given a pair of circuits to be verified, the filter approach first subjects the circuits to very simple, fast techniques having very low memory usage requirements. These steps are followed by a series of increasingly powerful methods that are more time consuming and often require more computer memory for their operation. In between the simpler active filters and the more sophisticated active filters, information about potential equivalent nodes in the circuits is collected and a decision is made as to whether to partition the circuits. The verification methodology is structured such that circuit designs that are easier to verify are never unnecessarily subjected to more expensive techniques. The method provides for a gradual increase in the sophistication of verification techniques applied, according to the difficulty of the verification problem.

Analog and mixed-signal test

Abstract: List of Figure. List of Tables. Preface. Contributors. 1. Introduction. Motivation. History. Current Research. Influence of Digital Test. Analog Test Issues. Test Paradigms. Organization. Conclusion. 2. Defect-Oriented Testing. Introduction. Previous Work. Estimation Method. Topological Method. Taxonomical Method. Defect-Based Realistic Fault Dictionary. Implementation. A Case Study. Fault Matrix Generation. Stimuli Matrix. Simulation Results. Silicon Results. Observations and Analysis. IFA-based Fault Grading and DFT for Analog Circuits. A/D Converter Testing. Description of the Experiment. Fault Simulation Issues. Fault Simulation Results. Analysis. DFT Measures. High-Level Analog Fault Models. Discussion: Strengths and Weaknesses of IFA-Based Tests. 3. Fault Simulation. Introduction. Why Analog Fault Simulation? Analog Fault Models and What-if Analysis. Focus and Organization. Fault Simulation of Linear Analog Circuits. Householder's Formula. Discrete Z-domain Mapping. Fault Bands and Band Faults. Interval-Mathematics Approach. Summary. C Fault Simulation of Nonlinear Analog Circuits. The Complementary Pivot Method. Fault Simulation via One-Step Relaxation. Simulation by Fault Ordering. Handling Statistical Variations. Summary. Fault Co-Simulation with Multiple Levels of Abstraction. Mixed-Signal Simulators. Incorporating Behavioral Models in Fault Simulation. Fault Macromodeling and Induced Behavioral Fault Modeling. Statistical Behavioral Modeling. Remarks on Hardware Description Languages. Concluding Remarks. 4. Automatic Test Generation Algorithms. Introduction. Fundamental Issues in Analog ATPG. Structural Test Versus Functional Test. Path Sensitization. Measurement Impact on Test Generation. Simulation Impact on Test Generation. Test Generation Algorithms and Results. Functional Test Generation Algorithms. Structural Test Generation Algorithms. ATPG Based on Automatic Test Selection Algorithms. DFT-based Analog ATPG Algorithms. Conclusions. 5. Design for Test. Preliminaries. Analog Characteristics. Common Characteristics. Generic Test Techniques. Increased Controllability/Observability. A/D Boundary Control. System-Specific Test Techniques. Analog Scan. Boundary Scan. Macro-Based DFT. Operational Amplifiers. Data Converters. Filters. Quality Analysis. Preliminaries. Analysis. Analysis. Conclusion. 6. Spectrum-Based Built-in Self-Test. Introduction. Some Early BIST Schemes. On-Chip Signal Generation. Digital Frequency Synthesis. Delta-Sigma Oscillators. Fixed-Length Periodic Bit Stream. Parameter Analysis. Fast Fourier Transform. Sinewave Correlation. Bandpass Filters. Application: MADBIST. Baseband MADBIST. Baseband MADBIST Experiments. MADBIST for Transceiver Circuits. Conclusions and Future Directions. 7. Implementing the 1149.4 Standard Mixed-Signal Test Bus. Overview of 1149.1 and 1149.4186. Test Functions Needed to Implement 1149.4189. Test Capabilities That This Standard Facilitates. Resistance, Capacitance, and Inductance Measurement. Measuring DC Parameters of Inputs and Outputs. Differential Measurements. Bandwidth. Delay Measurement. Potential Benefits of Using This Standard. Costs of Implementing This Standard on an IC. Practical Circuits Compliant with the Standard (Draft 18). Achieving Measurement Accuracy. DC Measurement Errors. AC Measurement Errors. Noise. Lessons from Test ICs. IMP (International Microelectronics Products) IC. Matsushita IC. Conclusions. 8. Test Techniques for CMOS Switched-Current Circuits. Introduction. Current Copiers: Basic Building Blocks of SI Circuits. Structure and Operation. Testing Current Copiers. Testing of Switched-Current Algorithmic A/D Converters. Structure and Operation. Concurrent Error Detection (CED). Test Generation. BIST Design. Scan Structures: Design for Testability. Conclusion. Index.

Implicit test generation for behavioral VHDL models

Abstract: This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage, in particular when considering circuits with hard to detect faults.

A test pattern generation methodology for low power consumption

Abstract: This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the test pattern generation phase and selects a subset of sequences able to reduce the consumed power without reducing the fault coverage. The method is composed of three independent steps: redundant test pattern generation, power consumption measurement, optimal test sequence selection. The experimental results gathered on the ISCAS benchmark circuits show that our approach decreases the power consumption by 70% on average with respect to the original test pattern, generated ignoring the heat dissipation problem.

Accumulator based deterministic BIST

Abstract: Most built-in self test (BIST) solutions require specialized test pattern generation hardware which may introduce significant area overhead and performance degradation. Recently, some authors proposed test pattern generation on chip by means of functional units also used in system mode like adders or multipliers. These schemes generate pseudo-random or pseudo-exhaustive patterns for serial or parallel BIST. If the circuit under test contains random pattern resistant faults a deterministic test pattern generator is necessary to obtain complete fault coverage. In this paper it is shown that a deterministic test set can be encoded as initial values of an accumulator based structure, and all testable faults can be detected within a given test length by carefully selecting the seeds of the accumulator. A ROM is added for storing the seeds, and the control logic of the accumulator is modified. In most cases the size of the ROM is less than the size required by traditional LFSR-based reseeding approaches.

Built-in self testing of sequential circuits using precomputed test sets

Abstract: We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of flip-flops but few primary inputs. Such circuits are often encountered as embedded cores and filters for digital signal processing, and are inherently difficult to test. We show that statistical encoding of test sets can be combined with low-cost pattern decoding for deterministic BIST. This approach exploits recent advances in sequential circuit ATPG and unlike other BIST schemes, does not require access to gate-level models of the circuit under test. Experimental results show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time.

Tight integration of combinational verification methods

Abstract: Combinational verification is an important piece of most equivalence checking tools. In the recent past, many combinational verification algorithms have appeared in the literature. Previous results show that these algorithms are able to exploit circuit similarity to successfully verify large designs. However, none of these strategies seems to work when the two input designs are not equivalent. We present our combinational verification algorithm, with evidence, that is designed to be robust for both the positive and the negative problem instances. We also show that a tight integration of different verification techniques, as opposed to a coarse integration of different algorithm, is more effective at solving hard instances.

Deterministic BIST with multiple scan chains

Abstract: A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.

A novel test methodology for core-based system LSIs and a testing time minimization problem

Abstract: In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

Automated synthesis of large phase shifters for built-in self-test

Abstract: The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators. The algorithms presented in the paper synthesize in a time-efficient manner very large and fast phase shifters for built in self-test environment, with guaranteed minimal phase shifts between scan chains, and very low delay and area of virtually one 2-way XOR gate per channel.

Automatic test pattern generation for crosstalk glitches in digital circuits

Abstract: As clock speeds of current deep submicron design technologies increase over 1 GHz and metal line spacings narrow, unexpected crosstalk effects start to degrade the circuit performance significantly. It is important for the designer to test the effects before taping out the designs. Unfortunately, conventional tests for stuck-at or delay faults are not guaranteed to expose potential crosstalk effects. This paper presents an efficient methodology for generating test vectors to detect crosstalk glitch effects in digital circuits. The ATEG (Automatic Test Extractor for Glitch) algorithm uses the multiple backrace technique, and uses a "forward-evaluation" technique in its backtacking phase which searches for the "right" entry to select by propagating "suggested values" to minimize the number of backtracks. In the glitch propagation phase, we employ a criterion function which gives a metric for determining the propagation of a transitional signal at a given gate. Our experiments show that ATEG efficiently generates test vectors to create glitches at candidate nodes.

Integration of non-classical faults in standard March tests

Abstract: New fault models like the unrestored write and the false write through faults and suitable test algorithms have recently been developed by several authors. These tests are applied in addition to March tests. Since a March test algorithm can be implemented in many different ways and still be effective in detecting its target faults, we have what we call degrees of freedom in the test space. In this paper it is shown, that for commonly used memory organizations tests for the unrestored write and false write through faults can be integrated in March test sequences. It is shown how to design address sequence generators and address dependent data for March tests, that generate all the patterns required for the detection of those faults. The detection properties of the original March tests are retained. The additional overhead in terms of silicon area and timing for an on-chip realization of a built-in March self-test with the added fault detection features is negligible and the test application time remains unchanged.

New techniques for deterministic test pattern generation

Abstract: This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance.

A fast and low cost testing technique for core-based system-on-chip

Abstract: This paper proposes a new methodology for resting a core-based system-on-chip (SOC), targeting the simultaneous reduction of test area overhead and test application time. Testing of embedded cores is achieved using the transparency properties of surrounding cores. At the core level, testability and transparency can be achieved by reusing existing logic inside the core, and providing different versions of the core having different area overheads and transparency latencies. At the chip level, the technique analyzes the topology of the SOC to select the core versions that best meet the user's desired test area overhead and test application time objectives. Application of the method to example SOCs demonstrates the ability to design highly testable SOCs with minimized test area overhead, minimized test application time, or a desired trade-off between the two. Significant reduction in area overhead and test application time compared to an existing SOC testing technique is also demonstrated.

Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

Abstract: This paper presents the results for very detailed studies of pattern and timing-dependent failures from the 309 dies in the retest of an experimental test chip. 22 out of the 50 CUTs with pattern-dependent failures had test escapes if the test sets were reordered. Some timing-dependent failures became timing-independent combinational (TIC) defects at very low voltage. Multiple-detect single stuck fault test sets have high transition fault coverage. Most dies with TIC or non-TIC defects were close to gross failures or next to the wafer periphery.

Efficient BIST TPG design and test set compaction via input reduction

Abstract: A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

A design-for-testability technique for register-transfer level circuits using control/data flow extraction

Abstract: In this paper, we present a technique for extracting functional (control/data flow) information from register-transfer level controller/data path circuits, and illustrate its use in design for hierarchical testability of these circuits. This scheme does not require any additional behavioral information. It identifies a suitable control and data flow from the register-transfer level circuit, and uses it to test each embedded element in the circuit by symbolically justifying its precomputed test set from the system primary inputs to the element inputs and symbolically propagating the output response to the system primary outputs. When symbolic justification and propagation become difficult, it inserts test multiplexers at suitable points to increase the symbolic controllability and observability of the circuit. These test multiplexers are mostly restricted to off-critical paths. Testability analysis and insertion are completely based on the register-transfer level circuit and the functional information automatically extracted from it, and are independent of the data path bit width owing to their symbolic nature. Furthermore, the data path test set is obtained as a byproduct of this analysis without any further search. Unlike many other design-for-testability techniques, this scheme makes the combined controller-data path very highly testable. It is general enough to handle control-flow-intensive register-transfer level circuits like protocol handlers as well as data-flow intensive circuits like digital filters. It results in low area/delay/power overheads, high fault coverage, and very low test generation times (because it is symbolic and independent of bit width). Also, a large part of our system-level test sets can be applied at speed. Experimental results on many benchmarks show the average area, delay, and power overheads for testability to be 3.1, 1.0, and 4.2%, respectively. Over 99% fault coverage is obtained in most cases with two-four orders of magnitude test generation time advantage over an efficient gate-level sequential test pattern generator and one-three orders of magnitude advantage over an efficient gate-level combinational test pattern generator (that assumes full scan). In addition, the test application times obtained for our method are comparable with those of gate-level sequential test pattern generators, and up to two orders of magnitude smaller than designs using full scan.