Showing papers on "Automatic test pattern generation published in 2018"

Hardware Trojan Detection Using ATPG and Model Checking

Abstract: The threat of hardware Trojans' existence in inte-gratedcircuits has become a major concern in System-on-Chip (SoC) design industry as well as in military/defense organizations. There is an increased emphasis on finding effective ways to detect and activate hardware Trojans in current research efforts. However, state-of-the-art approaches suffer from the lack of completeness and scalability. Moreover, most of the existing methods cannot generate efficient tests to activate the potential hidden Trojan. In this paper, we propose an effective test generation approach which is capable of activating malicious functionality hidden in large sequential designs. Automatic test pattern generation (ATPG) works well on full-scan designs, whereas model checking is suitable for logic blocks without scan chain. Due to overhead considerations, partial-scan chain insertion is the standard practice today. Unfortunately, neither ATPG nor model checking is suitable for partial-scan designs. Our proposed hardware Trojan detection technique utilizes the combination of ATPG and model checking approaches. We use model checking on a subset of non-scan elements and ATPG on scan elements to avoid common pitfalls of running the original design using any one of these techniques. Experimental results demonstrate the effectiveness of tests generated by our proposed approach to detect Trojans on Trust-hub benchmarks.

ATPG-based cost-effective, secure logic locking

Abstract: The globalization of IC supply chain lead to the emergence of hardware security threats such as IP piracy, reverse engineering, overbuilding, and hardware Trojans. Among the techniques developed to mitigate these threats, logic locking offers the most versatile protection and is being actively researched. The most recent locking technique SFLL thwarts with provable and quantifiable security all the state-of-the-art attacks including SAT, AppSAT, and the removal attack. However, the implementation cost of SFLL can sometimes be prohibitive, as it lacks an automated framework that explores cost-effective implementation options. In this paper, we show how VLSI testing principles and tools can be adopted to automate critical steps in SFLL and minimize its cost. We propose “SFLL-fault” that utilizes fault injection driven synthesis to efficiently explore design options and ATPG to assess security levels. Our experimental results confirm the efficacy of our strategy; SFLL-fault can reduce the implementation cost by 35% compared to SFLL without compromising security.

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits

Abstract: Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.

Modeling and test generation for combinational hardware Trojans

Abstract: Due to globalization of semiconductor manufacturing, appearance of malicious circuitry known as hardware Trojan is now a recognized security threat. A Trojan may be added to the verified netlist without the knowledge of the designer or user causing unexpected malfunction or data theft when the device is in use. In this research we devise tests that would detect a Trojan in a manufactured chip. We recognize that a Trojan must escape manufacturing tests provided with the netlist by the designer. Based on the two parts of a Trojan, namely, a trigger derived as a Boolean function of any set of signals and a payload (typically, an XOR gate) inserted on a signal line, we develop a test generation model. A single-line trigger combined with a single payload line gives a set of 2K × (K − 1) Trojans in this model for a circuit with K signal lines. Tests for these are shown to be vectors that detect “conditional stuck-at” faults, for which we give a test generation algorithm using standard ATPG tools. The model allows us to define and measure a Trojan coverage metric for tests. Results show scalability of these tests, besides being more effective in detecting real Trojans than N-detect stuck-at test vectors or random vectors.

XLBIST: X-Tolerant Logic BIST

Abstract: Logic Built-In Self-Test (LBIST) is becoming a requirement for high-complexity, high-reliability ICs which are increasingly used in the automotive field. Traditionally, LBIST can only be applied when there are no unknown simulation values (Xs) which would render the LBIST signature unusable. Eliminating all Xs in large industrial designs, especially when containing third party hard IP blocks, can be difficult, and anticipating all possible X-sources can be impractical. We present an X-tolerant LBIST solution (XLBIST) which uses compressor/decompressor structures, including Xcontrol logic, that have already been inserted in the design for scan-compression deterministic patterns. Automatic test pattern generation (ATPG) leverages these structures to generate efficient XLBIST patterns. Patterns can be generated for any number (or density) of Xs, with resulting test coverage tradeoff. Results on industrial designs with high X densities demonstrate consistent XLBIST coverage.

Approximation-aware testing for approximate circuits

Abstract: A wide range of applications significantly benefit from the Approximate Computing (AC) paradigm in terms of speed or power reduction. AC achieves this by tolerating errors in the design. These errors are introduced into the design either manually by the designer or by approximate synthesis approaches. From here, the standard design flow is taken. Hence, the manufactured AC chip is eventually tested for production errors using well established fault models. To be precise, if the test for a test pattern fails, the AC chip is sorted out. However, from a general perspective this procedure results in throwing away chips which are perfectly fine taking into account that the considered fault (i.e. physical defect that leads to the error) can still be tolerated because of approximation. This can lead to a significant amount of yield loss. In this paper, we present an approximation-aware test methodology which can be easily integrated into the regular test flow. It is based on a pre-process to identify approximation-redundant faults. By this, we remove all potential faults that no longer need to be tested because they can be tolerated under the given error metric. Our experimental results and case studies on a wide variety of benchmark circuits show a significant potential for yield improvement.

An Efficient SAT-Based Test Generation Algorithm with GPU Accelerator

Abstract: This paper presents a novel framework comprises of a Propositional Satisfiability (SAT) encoder and solver. The framework responsible for generating and proving a simplified SAT-based formula of digital circuits for Automatic Test Pattern Generation (ATPG) proposes. The parallel algorithms introduced in this work are aimed at both combinational and sequential circuits and optimized on NVIDIA General-Purpose Graphics Processing Unit (GPGPU) paradigm. The SAT encoder presents an efficient method to apply the Boolean Constraint Propagation (BCP) on-the-fly while the generation is running on the GPU. The simplified formula is further proved for satisfiability using an improved parallel solver on GPU. The proposed encoder executes 93 times faster compared to the sequential counterpart. The test generation algorithm using the GPU-accelerated framework delivers about 5.86 speedup on an average compared to the state-of-the-art Lingeling solver. Moreover, the SAT encoder reduced the run time for fault detection by 6.53 and 11.42% on an average when applied to the proposed and the conventional CUD@SAT solvers, respectively, offering promising related work for the future research.

Staggered ATPG with capture-per-cycle observation test points

Abstract: This paper presents a new staggered test pattern generation scheme. It produces deterministic stimuli in the course of a test-per-clock-based process by using dedicated capture-per-cycle observation test points. These observation points, once inserted into a design, form dedicated scan chains with the capability of capturing test responses during shift cycles when other regular scan cells are loading test patterns. This new scan infrastructure enables one to generate more compact test patterns, reduce test pattern counts, systematically detect many additional faults, and keep the resultant silicon real-estate at the acceptable level. It appears that original scan cells of a design can provide good observability for staggered test patterns. Thus, capture-per-cycle observation test points are directly inserted at selected scan cells' inputs with a minimal impact on the design. Experimental results obtained for large industrial designs illustrate feasibility of the proposed ATPG and are reported herein.

Improving Power, Performance and Area with Test: A Case Study

Abstract: As more low power devices are needed for applications such as IOT, reducing power and area is becoming more critical. Reducing power consumption and area caused by using full scan should be considered as a method to help achieve these stricter requirements. This is especially important in designs using near-threshold technology. In this work, we use partial scan to attempt to improve power, performance and area on a CPU core and a GPU shader core. We present our non-scan DFF selection algorithm that maximizes non-scan DFF count while achieving ATPG results close to those of the full scan design on both a CPU and a GPU shader core. In addition, we present the PPA (power, performance and area) results of these designs for both the full scan and partial scan.

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits

Abstract: Approximate Computing (AxC) emerges more and more as a new paradigm for the design of energy-efficient Integrated Circuits (ICs) at the cost of accuracy reduction. The latter has to be modeled and quantified by means of Error Metrics. From the testing point of view, AxC Integrated Circuits offer an opportunity. Instead of testing for all manufacturing defects, the goal is to test only for those that will lead to an error considered as not acceptable by the adopted Error Metrics. The main advantages are the test cost reduction, since the number of required test vectors will be reduced, and the yield improvement. We developed three approaches for generating test vectors targeting AxC Integrated Circuits. This paper aims at comparing these approaches on a public benchmark suite.

Hardware Protection via Logic Locking Test Points

Abstract: Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of which logic locking is a vital part. It allows inserting certain gates in a circuit’s data path to lock outputs to fixed logic values, if a wrong unlocking key is applied. This paper demonstrates that test points—industry-proven design-for-test technology used primarily to enhance the overall design testability–can also be reused in the mission mode to lock the circuit, and thus to improve the hardware security against IP piracy. In particular, it is shown that test points can facilitate the hiding of design functionality from adversaries. As a result, not only is the overall design testability improved, but also effective protection against piracy through unauthorized excess production and other forms of IP theft is ensured. Experimental results on industrial designs with test points demonstrate that the proposed scheme is effective in achieving a desired degree of hardware obfuscation.

An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults

Abstract: As fabricated circuitry becomes larger and denser, the modern industrial automatic test pattern generation techniques, which focus on the detection of single faults, become more likely to overlook multiple (simultaneous) faults. Although there are exponentially more multiple faults than single faults in any given circuit design, only a few additional test patterns are needed to cover all of the multiple faults, if the test generation starts from the complete test set for single faults. In this paper, we first show the case where test patterns for single faults are sufficient to cover all multiple faults, and then explain in which conditions some of the multiple faults may be overlooked. Based on this analysis, we propose a method that can efficiently generate the complete test set for double faults without traversing all the faults. Since most of the double faults can be detected by the single faults’ test set, the proposed method only selects the uncovered double faults by analyzing the propagation paths of single faults, and then generating new test patterns only for those uncovered faults. The experimental results show that based on the single faults’ test set, the proposed method only needs to create a small number of additional test patterns to cover all double faults in most of the given circuits. By repeating the same process, the proposed method can be incrementally applied to deal with all multiple faults.

Challenges in Cell-Aware Test

Abstract: Physical defects like opens and bridging defects can occur during the fabrication process of integrated circuits. The logic level abstraction of these physical defects, named fault models like stuck-at, transition, bridge, and small-delay defect, have been proposed, and are widely used in the industry for Automatic Test Pattern Generation (ATPG). However, as the technology moves to increasingly smaller geometries, these fault models and their associated test patterns are becoming less effective. The reason behind this is that existing fault models only consider faults on cell inputs and outputs, plus the interconnects between them. A growing number of defects occur within the cells, which are not explicitly targeted by traditional ATPG. N-detect algorithms can potentially test such defects by generating multiple patterns which detect cell-internal defects randomly. Cell-Aware Test (CAT) tries to solve this problem by uniquely targeting every possible internal defect. This is done via a series of analog simulations of all possible input combinations for all identified possible defects, which come at a significant runtime penalty. This paper shows a comparison of the static and transition patterns that are generated by the CAT methodology and the traditional ATPG for different library and cell parameters. This paper also aims to throw light on the quality concerns of the generated User Defined Fault Model (UDFM) by comparing results while varying different parameters of analog simulations, which reflect the variation due to Process, Voltage and Temperature (PVT). The increase in performance, pattern count and test coverage with respect to two Arm designs is also presented, which reflects the actual cost and gains of the CAT model over traditional ATPG.

Detection and Diagnosis of Single Faults in Quantum Circuits

Abstract: Detection and isolation of faults is a crucial step in the physical realization of quantum circuits. Even though quantum gates and circuits compute reversible functions, the standard techniques of automatic test pattern generation (ATPG) for classical reversible circuits are not directly applicable to quantum circuits. For faulty quantum circuits under the widely accepted single fault assumption, we show that their behavior can be fully characterized by the (single) faulty gate and the corresponding fault model. This allows us to efficiently determine test input states as well as measurement strategy for fault detection and diagnosis. Building on top of these, we design randomized algorithms which are able to detect every nontrivial single-gate fault with minimal probability of error. We also describe similar algorithms for fault diagnosis. We evaluate our algorithms by the number of output samples that needs to be collected and the probability of error. Both of these can be related to the eigenvalues of the operators corresponding to the circuit gates. We experimentally compare all our strategies with the state-of-the-art ATPG techniques for quantum circuits under the “single missing faulty gate” model and demonstrate that significant improvement is possible if we can exploit the quantum nature of circuits.

Input vulnerability-aware approximate triple modular redundancy: higher fault coverage, improved search space, and reduced area overhead

Abstract: Area overhead reduction in conventional triple modular redundancy (TMR) by using approximate modules has been proposed in the literature. However, the vulnerability of approximate TMR (ATMR) in the case of a critical input, where faults can lead to errors at the output, is yet to be studied. Here, identifying critical input space through automatic test pattern generation and making it unavailable for the technique of approximating modules of TMR (ATMR) were focused, which involves a prime implicant reduction expansion. The results indicate that the proposed method provides 75–98% fault coverage, which amounts up to 43.8% improvement over that achieved previously. The input vulnerability-aware approach enables a drastic reduction in search space, ranging from 41.5 to 95.5%, for the selection of candidate ATMR modules and no compromise on the area overhead reduction is noticed.

Scan-Chain Intra-Cell Aware Testing

Abstract: This paper first presents an evaluation of the effectiveness of different test pattern sets in terms of ability to detect possible intra-cell defects affecting the scan flip-flops. The analysis is then used to develop an effective test solution to improve the overall test quality. As a major result, the paper demonstrates that by combining test vectors generated by a commercial ATPG to detect stuck-at and delay faults, plus a fragment of extra test patterns generated to specifically target the escaped defects, we can obtain a higher intra-cell defect coverage (i.e., 6.46 percent on average) and a shorter test time (i.e., 42.20 percent on average) than by straightforwardly using an ATPG which directly targets these defects.

Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits

Abstract: Approximate Computing (AxC) is increasingly becoming a new design paradigm for energy-efficient Integrated Circuits (ICs). Specifically, application resiliency allows a tradeoff between accuracy and efficiency (energy/area/performance). Therefore, in recent years, Error Metrics have been proposed to model and quantify such accuracy reduction. In addition, Error thresholds are usually provided for defining the maximum allowed accuracy reduction. From a testing point of view, Approximate Integrated Circuits offer several opportunities. Indeed, approximation allows one to individuate a subset of tolerable faults, which are classified according to the adopted threshold. Thanks to fewer required test vectors, one achieves test-cost reduction and improvements in yield. Therefore, using metrics based on the calculation of Mean Errors (ME metrics), has become a major testing challenge. In this paper, we present this problem and investigate the technical requirements necessary for ME metric testing. We perform experiments on arithmetic circuits to study opportunities and challenges in terms of complexity. Our results show that one can filter up to 21% of faults and also highlight the complexity of the problem in terms of execution-time.

Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors

Abstract: An approach to detect ultra-low-power no-payload Trojans by analyzing IDDT waveforms at each gate is presented. The approach uses a novel ATPG to insert small number of current sensors in order to analyze the behavior of individual gates at the IDDT waveform. The proposed method is assisted by a standard cell placement method that strengthens Trojan detection. Experimental results on the largest ISCAS'85, ISCAS'89 and ITC'99 benchmarks demonstrate that low-power no-payload Trojans are detected without any area overhead and with negligible performance degradation.

Parallel order ATPG for test compaction

Abstract: In this paper, we proposed a novel test compaction algorithm, called Parallel Order Dynamic Test Compaction (PO-DTC). We show that the order of secondary faults within a single test generation is important for test compaction. We launch parallel ATPG with different orders of secondary faults and choose the best test pattern with the largest number of detected faults. Experimental results show that our test length is 48% shorter than that of a highly compacted commercial ATPG. Our test length is the smallest among all previous work published so far. Our test length for N-detect test sets is at least 1/4 shorter than that of the commercial ATPG.

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Abstract: Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux) We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole Algorithms to derive test set for multiple stuck-at faults are demonstrated The multiple stuck-at fault test set is larger than the single stuck-at fault test set We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage

An Efficient Technique to Reverse Engineer Minterm Protection Based Camouflaged Circuit

Abstract: Integrated circuit (IC) camouflaging technique has been applied as a countermeasure against reverse engineering (RE). However, its effectiveness is threatened by a boolean satisfiability (SAT) based de-camouflaging attack, which is able to restore the camouflaged circuit within only minutes. As a defense to the SAT-based de-camouflaging attack, a brand new camouflaging strategy (called CamoPerturb) has been proposed recently, which perturbs one minterm by changing one gate’s functionality and then restores the perturbed circuit with a separated camouflaged block, achieving good resistance against the SAT-based attack. In this paper, we analyze the security vulnerabilities of CamoPerturb by illustrating the mechanism of minterm perturbation induced by gate replacement, then propose an attack to restore the changed gate’s functionality, and recover the camouflaged circuit. The attack algorithm is facilitated by sensitization and implication principles in automatic test pattern generation (ATPG) techniques. Experimental results demonstrate that our method is able to restore the camouflaged circuits with very little time consumption.

Combinatorial Test Set Prioritization Using Data Flow Techniques

Abstract: Software testing is an expensive and important part of the software development process. One of the effective and cost- efficient test generation techniques is combinatorial testing, which identifies interaction faults that arise due to faulty combinations of few input parameters. However, for a large-sized system, it is practically impossible to execute the complete t-way test set due to time or resources constraints. As a result, only a portion of the test set can be executed leading to possible loss of fault detection capability. Prioritizing the test set helps in improving the fault detection capability. In this paper, prioritization of combinatorial test set is proposed using data flow technique. Different methods of prioritization criterion are proposed, and their effectiveness is compared by taking two software subjects. The effectiveness is compared by measuring percentage of pairs covered, percentage of weight covered and rate of fault detection. Computational results indicate that prioritized t-way test set achieves better fault detection rate as compared to unordered t-way test set.

Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits

Abstract: The application of scan-based at-speed delay testing on asynchronous circuits is not trivial. Their unorthodox design leaves them generally incompatible with traditional synchronous design and test tools, as well as standard automatic test equipment. The correct generation of at-speed test clocks and the use of conventional automatic test patterns generation (ATPG) tools are some of the problems that face the application of at-speed testing on asynchronous circuits. This paper presents a method of applying scan-based at-speed testing on single-rail bundleddata handshake-free (self-timed) asynchronous circuits by taking advantage of built-in delay lines. The proposed test method uses launch-on-capture scan-based testing with endpoint masking and generates the test patterns using conventional ATPG tools. The proposed test is applied on circuits in a self-timed microprocessor fabricated in 28nm FD-SOI CMOS technology. This method is validated by the reported test coverage and simulation results, along with post-silicon test results on a Teradyne FLEX tester.

Clock-Less DFT-Less Test Strategy for Null Convention Logic

Abstract: Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or sometimes they only affect the circuit by early detection of completeness. This work first proposes a clock-less self-timed ATPG, with no added design for test (DFT), that detects all of the faults on the gate inputs and a share of those on the GIF of gates. Then, this work investigates the effectiveness of I_DDQ (quiescent current) test for detecting stuck-at faults on GIF of NCL gates. Hspice is used for implementing static and semi-static transistor-level NCL gates in (45 nm, 1.1 V) technology, for which the supply current is measured and compared for fault-free and faulty circuits. The experimental results show that the faulty current is orders of magnitude higher than the fault-free leakage current. This considerable difference shows that I_DDQ testing might be an efficient and low-cost candidate for detecting stuck-at faults on GIF of NCL gates. The proposed I_DDQ test method along with the self-timed ATPG has resulted in average 98.16 and 98.04 percent fault coverage for static and semi-static implementations of several NCL circuits, respectively. To the extent of our knowledge, this is the first work that has addressed clock-less, self-timed ATPG for NCL with no area overhead, and also the first work conducted on I_DDQ test for NCL.

Logic Testing for Hardware Trojan Detection

Abstract: In this chapter, we describe effective logic testing algorithms for relatively small (less than ten two-input NAND gate equivalent) hardware Trojan detection. Conventional post-manufacturing testing, test generation algorithms, and test coverage metrics cannot be readily extended to hardware Trojan detection. To reduce this lacuna, a novel test pattern generation technique termed multiple excitation of rare occurrence (MERO) is introduced, which maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Extending this approach and addressing some of the shortcomings of MERO, an enhanced automatic test pattern generation (ATPG) scheme using genetic algorithm and Boolean satisfiability is described and evaluated.

Characterization of possibly detected faults by accurately computing their detection probability

Abstract: With ever more complex and larger VLSI devices and higher and higher reliability requirements, high quality test with a large fault and defect coverage is becoming even more relevant. At the same time, when unspecified or unknown input values (X values) have to be considered in a pattern, commercial ATPG tools are sometimes not capable of determining whether a fault can be tested — but there is at least a chance to detect the fault, as 0/X or 1/X could be propagated to at least one output. Consequently, these faults are considered to be possibly detected and often counted towards the overall fault coverage with a weighting factor. However, as the actual probability to detect these faults with the considered test pattern is not taken into account, this could lead to an over-or underestimation of their real fault coverage, falsifying the test results. We introduce a #SAT-based characterization algorithm for this class of faults. This new algorithm is, for the first time, able to accurately compute the detection probability for faults marked as possibly detected by state-of-the-art commercial tools. Our experimental results for the largest ITC'99 benchmarks as well as larger industrial-circuits show that our algorithm can accurately determine the detection probability for most of the possibly detected faults and also identify faults that are completely untestable or found with a probability of 100 % irrespective of the assignment of the inputs with an X value. Furthermore, they show that the detection probability is circuit-dependent and consequently should not just be estimated by a simple weighting factor but requires a more in-depth evaluation. Otherwise, there is a high risk that the achieved results could clearly be to optimistic or pessimistic with regard to the real fault coverage.

Optimization of threshold logic networks with ODC-based node merging

Abstract: In this paper, we present an optimization method for threshold logic networks (TLNs) based on observability don't care (ODC)-based node merging. The method is adapted from an ATPG-based node-merging approach that works for conventional Boolean logic networks. To extend the approach for TLNs, we propose a method for computing the mandatory assignments of a stuck-at fault test on a threshold gate and a method for conducting logic implication in a TLN. The experimental results show that the proposed optimization method can save an average of approximately 2% threshold gates for a set of TLNs which are generated by using the latest TLN synthesis approach. The experimental results also demonstrate the efficiency of the proposed optimization method.

Hypercompression of Test Patterns

Abstract: The paper presents a novel test data compression scheme. This low-silicon-area solution builds on the isometric compression paradigm, but makes it more flexible, elevates encoding efficiency to values unachievable through any conventional type of sequential compression, and ensures high test coverage due to programmable selection of full toggle scan chains. The presented approach follows from a fundamental observation that only a few specified positions in test cubes are necessary to detect faults, while the remaining ones have alternative sites. Such test cubes are used to form circular test templates which synergistically control a decompressor and guide ATPG to find assignments yielding highly compressible test cubes. A redesigned decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. Experimental results obtained for large industrial designs confirm superiority of the proposed scheme over state-of-the-art techniques and are reported herein.

Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run

Abstract: This paper presents a novel test pattern generation flow to detect stuck-at and transition faults simultaneously. Both fault models are transformed into a unified fault model for a proposed 2-time-frame circuit model. This makes it possible to generate patterns for both types of faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set can thus be obtained which requires less test data volume and shorter test application time without degrading the fault coverage for either type of faults. Experimental results show that, compared to the conventional methods, the proposed method can reduce the total test pattern counts by up to 12.27% and 15.54% and test application times up to 12.06% and 15.58% for ISCAS'89 and ITC'99 circuits, respectively.