Showing papers on "Automatic test pattern generation published in 2021"

C-Testing and Efficient Fault Localization for AI Accelerators*

Abstract: Accelerators for machine learning (AI) inferencing applications are homogeneous designs composed of identical cores. Each core, or processing element (PE), contains multiply-and-accumulate units, control logic, and registers for storing and forwarding weights and activations. Testing homogeneous array-based AI accelerator chips by running automatic test pattern generation (ATPG) at the array level results in a high CPU time and pattern count. We propose a constant-testable (C-testable) method for test generation at the PE level such that the ATPG effort does not increase with the number of PEs. Our results show that, compared to the traditional array-level testing, the proposed method achieves up to 4.2× (3.5×), 1530× (2388×), and 170× (142×) reduction in the test pattern count, ATPG runtime, and test cycle count, respectively, for stuck-at (transition) faults in a 256×256 array, while preserving the test coverage. A reconfigurable scan architecture is introduced to enable the proposed C-testable solution for the entire accelerator array. The design-space exploration of a hierarchical test-compaction framework is presented. We also describe four debug solutions for fault localization and diagnosis.

Test and Yield Loss Reduction of AI and Deep Learning Accelerators

Abstract: With data-driven analytics becoming mainstream, the global demand for dedicated AI and Deep Learning accelerator chips is soaring. These accelerators, designed with densely packed Processing Elements (PE), are especially vulnerable to the manufacturing defects and functional faults common in the advanced semiconductor process nodes resulting in significant yield loss. In this work, we demonstrate an application-driven methodology of binning the AI accelerator chips, and yield loss reduction by correlating the circuit faults in the PEs of the accelerator with the desired accuracy of the target AI workload. We exploit the inherent fault tolerance features of trained deep learning models and a strategy of selective deactivation of faulty PEs to develop the presented yield loss reduction and test methodology. An analytical relationship is derived between fault location, fault rate, and the AI task’s accuracy for deciding if the accelerator chip can pass the final yield test. A yield-loss reduction aware fault isolation, ATPG, and test flow are presented for the multiply and accumulate units of the PEs. Results obtained with widely used AI/deep learning benchmarks demonstrate that the accelerators can sustain 5% fault-rate in PE arrays while suffering from less than 1% accuracy loss, thus enabling product-binning and yield loss reduction of these chips.

Defect-Oriented Test: Effectiveness in High Volume Manufacturing

Abstract: This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.

Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator

Abstract: Recent research shows that an artificial neural network (ANN) can combine multiple heuristics to guide an automatic test pattern generator (ATPG) with fewer backtracks than required by guidance from any single heuristic. Thus motivated, we develop a new training method to include multiple heuristics. Our ANN has a single output neuron and a single layer of hidden neurons, which is sufficient to accommodate the training data volume. Conventional PODEM ATPG applied to hard-to-detect and easily detectable faults in selected benchmark circuits provide training data for nodes marked as “success” if the backtrace leads to a test or “failure” if it results in backtrack. ATPG data of a fault is used for training only if backtracks in the ANN -guided ATPG decrease. Circuit parameters added to training include input-output distances and testability values from COP (controllability and observability program) for signal nodes. Compared to the ANN guidance in previous studies, the proposed training method is found to require fewer total backtracks for all faults in any circuit from ISCAS'85 and ITC'99 benchmarks.

Unsupervised Learning in Test Generation for Digital Integrated Circuits

Abstract: The exponential complexity of automatic test pattern generation (ATPG) necessitates the use of heuristics in making choices during test generation. However, in practice no single heuristic fits all situations. Unsupervised learning can combine any number of known heuristics, such as input-output distance (logic depths), gate type, fanout information, and testability measures like Controllability and Observability Program (COP) and Sandia Controllability/Observability Analysis Program (SCOAP) through principal component (PC) analysis, and then the major PC can guide ATPG choices. This study combines three heuristics, distance, COP, and SCOAP. Some heuristic data are complemented and two major PC are obtained. These PC guide backtrace directions in a PODEM ATPG program. For most circuits, the number of backtracks either matches the best of the three heuristics or is lower than all.

Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures

Abstract: With the explosion of off-the-shelf SoCs in terms of size and the advent of novel techniques related to failure modes, commercial ATPG and fault simulation engines can often be insufficient to measure the coverage of very specific metrics. In these cases, many researchers firstly store the simulation trace during the analysis phase. Then, they collect the desired statistics during a post-processing step. In this framework, the so-called Value Change Dump (VCD) is a very commonly used file format to record simulation traces. The target of this paper is twofold. From the one hand, we illustrate some Burn-In (BI) related metrics which cannot be evaluated by current commercial fault simulators and ATPG engines. These metrics are indeed based on a post-processing analysis of memory dumps in VCD format. From the other hand, we mitigate the evaluation time and the memory required to analyze huge VCD files by exploiting optimization techniques coming from modern programming features and smart parallelization. Adopting this strategy, we can analyze simulation dumps of more than 250 GBytes in less than one hour, showing improvements of two orders of magnitude over previous tools, with a consequent higher scalability and testability power.

Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits

Abstract: Sensitivity to process variations and manufacturing defects are major showstoppers for the high-volume manufacturing of carbon nanotube field-effect transistors (CNFETs). These imperfections affect gate delay and may remain undetected when test patterns obtained using conventional test-generation techniques are used. We propose a new test generation method that takes CNFET-specific process variations into account and identifies multiple testable long paths through each node in a netlist. In contrast to state-of-the-art techniques, our method can also handle variations that have a nonlinear impact on the propagation delay. The generated test patterns ensure the detection of delay faults through the longest path, even under random CNFET process variations. The proposed method shows significant improvement in the statistical delay quality level (SDQL) compared with a state-of-the-art technique and a commercial ATPG tool for multiple benchmarks. We observed a minimum of 17.1% improvement in the SDQL offered by our patterns over a test set of the same size generated by the commercial tool. We also show that our method, when integrated with the conventional transition fault test flow, offers a significant improvement in the quality of test patterns under random variations. Moreover, the proposed method is flexible and can be easily extended to other emerging device technologies.

Principal Component Analysis in Machine Intelligence-Based Test Generation

Abstract: In a machine intelligence (MI)-based automatic test pattern generator (ATPG), an artificial neural network (ANN) may guide decisions that would otherwise rely on some heuristic. Heuristics use circuit-specific data such as gate types, logic depth, fan-out data, or various testability measures. Treating these data collectively as a multivariate statistic of circuit topology, this study extracts principal components (PCs). A subset of PCs is then used to train the ANN that facilitates algorithmic decisions in ATPG. This reduces the ANN complexity and enhances ATPG efficiency. Results on benchmark circuits show the benefit of reduced CPU time.

High-level Intellectual Property Obfuscation via Decoy Constants

Abstract: This paper presents a high-level circuit obfuscation technique to prevent the theft of intellectual property (IP) of integrated circuits. In particular, our technique protects a class of circuits that relies on constant multiplications, such as filters and neural networks, where the constants themselves are the IP to be protected. By making use of decoy constants and a key-based scheme, a reverse engineer adversary at an untrusted foundry is rendered incapable of discerning true constants from decoy constants. The time-multiplexed constant multiplication (TMCM) block of such circuits, which realizes the multiplication of an input variable by a constant at a time, is considered as our case study for obfuscation. Furthermore, two TMCM design architectures are taken into account; an implementation using a multiplier and a multiplierless shift-adds implementation. Optimization methods are also applied to reduce the hardware complexity of these architectures. The well-known satisfiability (SAT) and automatic test pattern generation (ATPG) attacks are used to determine the vulnerability of the obfuscated designs. It is observed that the proposed technique incurs small overheads in area, power, and delay that are comparable to the hardware complexity of prominent logic locking methods. Yet, the advantage of our approach is in the insight that constants -- instead of arbitrary circuit nodes -- become key-protected.

Developing Benchmarks for Radiation Testing of Microcontroller Arithmetic Units Using ATPG

Abstract: Reliability-focused benchmarks are used to test systems in harsh operating conditions, including space and terrestrial radiation environment. The sensitivity to single-event effects of a microprocessor in a radiation environment depends on the set of input vectors used at the time of testing due to logical masking. This article analyzes the impact of the input test set on the cross section of the microprocessor and proposes a mechanism to derive a high-quality input test set using automatic test pattern generation (ATPG) for radiation testing of microprocessor’s arithmetic and logical units.

Defect Characterization and Testing of Skyrmion-Based Logic Circuits

Abstract: Magnetic skyrmion is an emerging digital technology that provides ultra-high integration density and requires ultralow energy. Skyrmion is a magnetic pattern behaving like a stable pseudoparticle, created by a transverse current injection in ferromagnetic thin film. The state of a logic signal is represented by the presence (logic-l) or absence (logic-0) of a single skyrmion. Patterns on ferromagnetic and metal films form interconnects, called nanotracks, through which electric currents move skyrmions. Because skyrmion-based logic gates (e.g., AND, OR, inverter, and fanout) operate through skyrmion-to-skyrmion interaction, their logic circuit implementation and manufacturing defects differ from those of CMOS circuits. We examine breaks and bridges in nanotrack interconnects, and 19 technology-specific defects in skyrmion gate structures. Simulator $Mu{\rm Max}^{3}$ is used to exhaustively simulate all circuit elements. The results help map each defect onto a fault, modeled in an equivalent logic circuit. A break in a nanotrack interconnect maps onto a single stuck-at fault. Experiments on benchmark circuits demonstrate that tests for all nanotrack breaks can be found using the available ATPG and simulation tools. Others are classified as technology-specific defects. For example, a bridge between two nanotracks results in simultaneous AND and OR functions on respective nanotracks. A variety of technology-dependent faults are identified for future research.

High-level Intellectual Property Obfuscation via Decoy Constants

Abstract: This paper presents a high-level circuit obfuscation technique to prevent the theft of intellectual property (IP) of integrated circuits. In particular, our technique protects a class of circuits that relies on constant multiplications, such as neural networks and filters, where the constants themselves are the IP to be protected. By making use of decoy constants and a key-based scheme, a reverse engineer adversary at an untrusted foundry is rendered incapable of discerning true constants from decoys. The time-multiplexed constant multiplication (TMCM) block of such circuits, which realizes the multiplication of an input variable by a constant at a time, is considered as our case study for obfuscation. Furthermore, two TMCM design architectures are taken into account; an implementation using a multiplier and a multiplierless shift-adds implementation. Optimization methods are also applied to reduce the hardware complexity of these architectures. The well-known satisfiability (SAT) and automatic test pattern generation (ATPG) based attacks are used to determine the vulnerability of the obfuscated designs. It is observed that the proposed technique incurs small overheads in area, power, and delay that are comparable to the hardware complexity of prominent logic locking methods. Yet, the advantage of our approach is in the insight that constants - instead of arbitrary circuit nodes - become key-protected.

Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis

Abstract: The test of digital circuits has benefitted greatly from the adoption of logical fault models and automatic test pattern generation (ATPG) tools targeting them. The cyclic process of defects in newer technology nodes being increasingly missed out by gross fault models and newer fault models being developed to better target them in silicon has continued, and EDA tools have evolved to provide new automation capabilities. This paper presents silicon results on one of Texas Instruments' new safety critical products which show unique defect detection with patterns targeting newer fault models like small delay defects (SDD) and cell aware faults (CAF), and RAM Sequential (RAM-S) ATPG patterns for memory faults. The net defective parts per million (DPPM) recovered using these methods is 72. Based on these results, recommendations for coverage targets and the order in which these faults must be targeted are provided. The unique silicon fall-out data presented in this paper provides a strategy for very low (zero) DPPM test of digital systems-on-chips (SoCs) in advanced technology nodes.

Automatic Test Pattern Generation of Multiple stuck-at faults using Test Patterns of Single stuck-at faults

Abstract: The fabricated circuitries are getting massive and denser with every passing year due to which a normal automatic test pattern generation technique to detect only the single stuck-at faults will overlook the multiple stuck-at faults. But generating test patterns that can detect all possible multiple stuck-at fault is practically not possible. Hence, this paper proposes a method, where multiple faults can be detected by using test vectors for detecting single stuck-at faults. Here, the patterns for detecting single faults are generated and their ability to detect multiple stuck-at faults is also analyzed. From the experimental results it was observed that, the generated vectors for single faults cover maximum number of the multiple faults and then new test vectors are generated for the undetermined faults. The generated vectors are optimized for the compact test patterns in order to reduce the test power.

Advancement in Onchip Clocking to Improve ATPG Coverage Between Clock Domains

Abstract: Using multi-clock domain is much needed nowadays to lighten the complexity of System On Chip (SoC). To deliver high quality for a design testing is very much necessary to achieve higher test coverage for stuck at fault model as well as transition delay fault model. Things are not tough when we have to deal with flops driven with same clock domain. However, achieving good test coverage for TDF fault model when flops are driven by two different clock domain is a challenge. This paper proposes usage of synchronous On Chip Clock controller (OCC) to cover faults between two different synchronous clock domains and ensure high quality pattern generation for Transition Delay Fault (TDF). A sync OCC techniques that helps to improve ATPG coverage for by ~3% and pattern count reduction due to same in critical transition mode testing.

Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits

Abstract: It is a real challenge to test asynchronous circuits since there is no clock signal, and there are many non-scan state-holding elements. In this paper, we first propose an Asynchronous Circuit Scan (A-SCAN) latch, which can flip between Valid and Empty states so that we can shift in and out without any clock. Experimental results show that our DFT area and power overhead are 28% and 104% smaller than previous synchronous DFT, respectively. The timing overhead of DFT is nearly two times smaller than previous asynchronous DFT. Based on A-SCAN, we propose the Asynchronous Built-in Self Test (A-BIST), which has no clock. Experimental results show that our BIST area and power overhead are 30% and 116% smaller than previous synchronous counterpart, respectively. Our test coverage is similar to that of ATPG. With A-SCAN and A-BIST, we can easily integrate synchronous and asynchronous testing on the same chip.

GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer

Abstract: Test generation and fault simulation are essential in VLSI automatic test pattern generation (ATPG). Parallel computing on GPU gives another way to improve work performance. Thousands of concurrent threads can be launched simultaneously within GPU. Due to severe GPU memory limitation, scalability algorithm and efficient data transfer are necessary for test generation and fault simulation. In this paper, we present a GPU-based ATPG system that can scale memory usage and reduce data transfer between processors. We utilize several parallelism methods to enhance the system ability. Comparing to a commercial tool run with CPU in single, two, four, and eight cores, experiments show that our algorithm has 3.99, 2.18, 1.17 and 0.94 times of speedup and 0.85, 0.78, 0.76 and 0.73 times of less memory usage, respectively.

Testability-Aware Low Power Controller Design with Evolutionary Learning

Abstract: XORNet-based low power controller is a popular technique to reduce circuit transitions in scan-based testing. However, existing solutions construct the XORNet evenly for scan chain control, and it may result in sub-optimal solutions without any design guidance. In this paper, we propose a novel testability-aware low power controller with evolutionary learning. The XORNet generated from the proposed genetic algorithm (GA) enables adaptive control for scan chains according to their usages, thereby significantly improving XORNet encoding capacity, reducing the number of failure cases with ATPG and decreasing test data volume. Experimental results indicate that under the same control bits, our GA-guided XORNet design can improve the fault coverage by up to 2.11%. The proposed GA-guided XORNets also allows reducing the number of control bits, and the total testing time decreases by 20.78% on average and up to 47.09% compared to the existing design without sacrificing test coverage.

Diagnosis resolution prediction

Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to generate test patterns to apply to scan chains in an integrated circuit. The computing system can implement a defect diagnosis tool to simulate a circuit design describing an integrated circuit, inject faults from a fault list into the simulated circuit design, and apply the test patterns to the simulated circuit design. The computing system implementing the defect diagnosis tool can determine fault responses to the test patterns read from the simulated circuit design, which indicate a detection of the faults injected in the simulated circuit design, compress, for each of the faults in the fault list, the fault responses into fault signatures, consolidate the faults from the fault list into fault groups based on the fault signatures, and estimate a diagnosis resolution for the integrated circuit based, at least in part, on the fault groups.

Automatic Test Pattern Generation using Grover’s Algorithm

Abstract: Quantum computing is an exciting new field in the intersection of computer science, physics and mathematics. It refines the central concepts from Quantum mechanics into its least difficult structures, peeling away the complications from the physical world. Any combinational circuit that has only one stuck at fault can be tested by applying a set of inputs that drive the circuit to verify the output response. The outputs of that circuit will be different from the one desired if the faults exist. This project describes a method of generating test patterns using the Boolean satisfaction method. First, the Boolean formula is constructed to express the Boolean difference between a fault-free circuit and a faulty circuit. Second, the Boolean satisfaction algorithm is applied to the formula in the previous step. The Grover algorithm is used to solve the Boolean satisfaction problem. The Boolean Satisfiability problem for Automatic Test Pattern Generation(ATPG) is implemented on IBM Quantum Experience. The Python program initially generates the boolean expression from the file and converts it into Conjunctive Normal Form(CNF) which is passed on to Grover Oracle and runs on IBM simulator and produces excellent results on combinational circuits for test pattern generation with a quadratic speedup. Grover’s Algorithm on this problem has a run time of O(√N).

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Abstract: Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test pattern generation (ATPG) approaches, which target faults only at the boundaries of library cells. The CAT methodology consists of two stages. Stage 1, based on dedicated analog simulation, library characterization per cell identifies which cell-level test pattern detects which cell-internal defect; this detection information is encoded in a defect detection matrix (DDM). In Stage 2, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells. This paper focuses on Stage 1, library characterization, as both test quality and cost are determined by the set of cell-internal defects identified and simulated in the CAT tool flow. With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to as full set, of potential open- and short-defect locations based on cell layout. However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage 1 unaffordable. Subsequently, to reduce the simulation time, we collapse the full set to a compact set of defects which serves as input of the defect simulation. The full set is stored for the diagnosis and failure analysis. With inspecting the simulation results, we propose a method to verify the test quality based on the compact set of defects and, if necessary, to compensate the test quality to the same level as that based on the full set of defects. For 351 combinational library cells in Cadence’s GPDK045 45nm library, we simulate only 5.4% defects from the full set to achieve the same test quality based on the full set of defects. In total, the simulation time, via linear extrapolation per cell, would be reduced by 96.4% compared with the time based on the full set of defects.

Accelerating GLS Simulation closure in DFT with Emulator

Abstract: To keep pace with the demands of advanced complex SoC development and to close the HW /SW verification gap, Emulation is increasingly used as a scalable and reusable solution. As part of a quicker execution schedule, DFT Engineers deploy optimum methods of RTL, ATPG, MBIST verification, and even proto-type complete RTL into Emulator for faster RTL verification closure. Another integral part of DFT verification is Gate-Level Simulation of MBIST and ATPG patterns but done in small volume due to huge simulator-time requirement leading to incomplete closure. We propose vector-mode based Gate level emulation (GLE) for DFT patterns. This paper talks about 500-to-1500X performance gain when simulating MBIST and ATPG complete pattern set in Emulator over GLS. Results show that for 2 SOCs of size 36M, 55M gates, a complete stuck-at, and transition ATPG WGL format pattern set of 90k can be simulated in Emulator within hours. Manufacturing Algorithm-based MBIST WGL patterns which take weeks in the EDA simulator can be emulated in minutes. This provides closure of DFT Pre-silicon GLS Verification within a day. The verified WGL patterns can be seamlessly ported to ATE Tester program for post-silicon Bring-up, bridging the verification gap between RTL and silicon device. The paper also shows a method of debugging ATPG and MBIST pattern failures with debug logs and waveforms dumped from the Emulator program.

Test Coverage Analysis of DFT with EDT and without EDT Architecture

Abstract: ATPG is one of the well-defined technique for generating test patterns for testing the chips. Today's world of SOC design environment, designs are complex so that the number of test patterns required for testing the chips increases. EDT (Embedded deterministic testing) is employed in order to reduce the test volume and reduced ATE memory usage due to large number of test patterns. This paper aims to determine, how well the EDT architecture performs in a DFT environment in terms of coverage for atspeed and stuck at fault model.