Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

Abstract: This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M

Improving test suites for efficient fault localization

Abstract: The need for testing-for-diagnosis strategies has been identified for a long time, but the explicit link from testing to diagnosis (fault localization) is rare. Analyzing the type of information needed for efficient fault localization, we identify the attribute (called Dynamic Basic Block) that restricts the accuracy of a diagnosis algorithm. Based on this attribute, a test-for-diagnosis criterion is proposed and validated through rigorous case studies: it shows that a test suite can be improved to reach a high level of diagnosis accuracy. So, the dilemma between a reduced testing effort (with as few test cases as possible) and the diagnosis accuracy (that needs as much test cases as possible to get more information) is partly solved by selecting test cases that are dedicated to diagnosis.

Syndrome-Testable Design of Combinational Circuits

Abstract: Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.

Digital logic testing and simulation

Abstract: Preface. 1 Introduction. 1.1 Introduction. 1.2 Quality. 1.3 The Test. 1.4 The Design Process. 1.5 Design Automation. 1.6 Estimating Yield. 1.7 Measuring Test Effectiveness. 1.8 The Economics of Test. 1.9 Case Studies. 1.9.1 The Effectiveness of Fault Simulation. 1.9.2 Evaluating Test Decisions. 1.10 Summary. Problems. References. 2 Simulation. 2.1 Introduction. 2.2 Background. 2.3 The Simulation Hierarchy. 2.4 The Logic Symbols. 2.5 Sequential Circuit Behavior. 2.6 The Compiled Simulator. 2.6.1 Ternary Simulation. 2.6.2 Sequential Circuit Simulation. 2.6.3 Timing Considerations. 2.6.4 Hazards. 2.6.5 Hazard Detection. 2.7 Event-Driven Simulation. 2.7.1 Zero-Delay Simulation. 2.7.2 Unit-Delay Simulation. 2.7.3 Nominal-Delay Simulation. 2.8 Multiple-Valued Simulation. 2.9 Implementing the Nominal-Delay Simulator. 2.9.1 The Scheduler. 2.9.2 The Descriptor Cell. 2.9.3 Evaluation Techniques. 2.9.4 Race Detection in Nominal-Delay Simulation. 2.9.5 Min-Max Timing. 2.10 Switch-Level Simulation. 2.11 Binary Decision Diagrams. 2.11.1 Introduction. 2.11.2 The Reduce Operation. 2.11.3 The Apply Operation. 2.12 Cycle Simulation. 2.13 Timing Verification. 2.13.1 Path Enumeration. 2.13.2 Block-Oriented Analysis. 2.14 Summary. Problems. References. 3 Fault Simulation. 3.1 Introduction. 3.2 Approaches to Testing. 3.3 Analysis of a Faulted Circuit. 3.3.1 Analysis at the Component Level. 3.3.2 Gate-Level Symbols. 3.3.3 Analysis at the Gate Level. 3.4 The Stuck-At Fault Model. 3.4.1 The AND Gate Fault Model. 3.4.2 The OR Gate Fault Model. 3.4.3 The Inverter Fault Model. 3.4.4 The Tri-State Fault Model. 3.4.5 Fault Equivalence and Dominance. 3.5 The Fault Simulator: An Overview. 3.6 Parallel Fault Processing. 3.6.1 Parallel Fault Simulation. 3.6.2 Performance Enhancements. 3.6.3 Parallel Pattern Single Fault Propagation. 3.7 Concurrent Fault Simulation. 3.7.1 An Example of Concurrent Simulation. 3.7.2 The Concurrent Fault Simulation Algorithm. 3.7.3 Concurrent Fault Simulation: Further Considerations. 3.8 Delay Fault Simulation. 3.9 Differential Fault Simulation. 3.10 Deductive Fault Simulation. 3.11 Statistical Fault Analysis. 3.12 Fault Simulation Performance. 3.13 Summary. Problems. References. 4 Automatic Test Pattern Generation. 4.1 Introduction. 4.2 The Sensitized Path. 4.2.1 The Sensitized Path: An Example. 4.2.2 Analysis of the Sensitized Path Method. 4.3 The D-Algorithm. 4.3.1 The D-Algorithm: An Analysis. 4.3.2 The Primitive D-Cubes of Failure. 4.3.3 Propagation D-Cubes. 4.3.4 Justification and Implication. 4.3.5 The D-Intersection. 4.4 Testdetect. 4.5 The Subscripted D-Algorithm. 4.6 PODEM. 4.7 FAN. 4.8 Socrates. 4.9 The Critical Path. 4.10 Critical Path Tracing. 4.11 Boolean Differences. 4.12 Boolean Satisfiability. 4.13 Using BDDs for ATPG. 4.13.1 The BDD XOR Operation. 4.13.2 Faulting the BDD Graph. 4.14 Summary. Problems. References. 5 Sequential Logic Test. 5.1 Introduction. 5.2 Test Problems Caused by Sequential Logic. 5.2.1 The Effects of Memory. 5.2.2 Timing Considerations. 5.3 Sequential Test Methods. 5.3.1 Seshu's Heuristics. 5.3.2 The Iterative Test Generator. 5.3.3 The 9-Value ITG. 5.3.4 The Critical Path. 5.3.5 Extended Backtrace. 5.3.6 Sequential Path Sensitization. 5.4 Sequential Logic Test Complexity. 5.4.1 Acyclic Sequential Circuits. 5.4.2 The Balanced Acyclic Circuit. 5.4.3 The General Sequential Circuit. 5.5 Experiments with Sequential Machines. 5.6 A Theoretical Limit on Sequential Testability. 5.7 Summary. Problems. References. 6 Automatic Test Equipment. 6.1 Introduction. 6.2 Basic Tester Architectures. 6.2.1 The Static Tester. 6.2.2 The Dynamic Tester. 6.3 The Standard Test Interface Language. 6.4 Using the Tester. 6.5 The Electron Beam Probe. 6.6 Manufacturing Test. 6.7 Developing a Board Test Strategy. 6.8 The In-Circuit Tester. 6.9 The PCB Tester. 6.9.1 Emulating the Tester. 6.9.2 The Reference Tester. 6.9.3 Diagnostic Tools. 6.10 The Test Plan. 6.11 Visual Inspection. 6.12 Test Cost. 6.13 Summary. Problems. References. 7 Developing a Test Strategy. 7.1 Introduction. 7.2 The Test Triad. 7.3 Overview of the Design and Test Process. 7.4 A Testbench. 7.4.1 The Circuit Description. 7.4.2 The Test Stimulus Description. 7.5 Fault Modeling. 7.5.1 Checkpoint Faults. 7.5.2 Delay Faults. 7.5.3 Redundant Faults. 7.5.4 Bridging Faults. 7.5.5 Manufacturing Faults. 7.6 Technology-Related Faults. 7.6.1 MOS. 7.6.2 CMOS. 7.6.3 Fault Coverage Results in Equivalent Circuits. 7.7 The Fault Simulator. 7.7.1 Random Patterns. 7.7.2 Seed Vectors. 7.7.3 Fault Sampling. 7.7.4 Fault-List Partitioning. 7.7.5 Distributed Fault Simulation. 7.7.6 Iterative Fault Simulation. 7.7.7 Incremental Fault Simulation. 7.7.8 Circuit Initialization. 7.7.9 Fault Coverage Profiles. 7.7.10 Fault Dictionaries. 7.7.11 Fault Dropping. 7.8 Behavioral Fault Modeling. 7.8.1 Behavioral MUX. 7.8.2 Algorithmic Test Development. 7.8.3 Behavioral Fault Simulation. 7.8.4 Toggle Coverage. 7.8.5 Code Coverage. 7.9 The Test Pattern Generator. 7.9.1 Trapped Faults. 7.9.2 SOFTG. 7.9.3 The Imply Operation. 7.9.4 Comprehension Versus Resolution. 7.9.5 Probable Detected Faults. 7.9.6 Test Pattern Compaction. 7.9.7 Test Counting. 7.10 Miscellaneous Considerations. 7.10.1 The ATPG/Fault Simulator Link. 7.10.2 ATPG User Controls. 7.10.3 Fault-List Management. 7.11 Summary. Problems. References. 8 Design-For-Testability. 8.1 Introduction. 8.2 Ad Hoc Design-for-Testability Rules. 8.2.1 Some Testability Problems. 8.2.2 Some Ad Hoc Solutions. 8.3 Controllability/Observability Analysis. 8.3.1 SCOAP. 8.3.2 Other Testability Measures. 8.3.3 Test Measure Effectiveness. 8.3.4 Using the Test Pattern Generator. 8.4 The Scan Path. 8.4.1 Overview. 8.4.2 Types of Scan-Flops. 8.4.3 Level-Sensitive Scan Design. 8.4.4 Scan Compliance. 8.4.5 Scan-Testing Circuits with Memory. 8.4.6 Implementing Scan Path. 8.5 The Partial Scan Path. 8.6 Scan Solutions for PCBs. 8.6.1 The NAND Tree. 8.6.2 The 1149.1 Boundary Scan. 8.7 Summary. Problems. References. 9 Built-In Self-Test. 9.1 Introduction. 9.2 Benefits of BIST. 9.3 The Basic Self-Test Paradigm. 9.3.1 A Mathematical Basis for Self-Test. 9.3.2 Implementing the LFSR. 9.3.3 The Multiple Input Signature Register (MISR). 9.3.4 The BILBO. 9.4 Random Pattern Effectiveness. 9.4.1 Determining Coverage. 9.4.2 Circuit Partitioning. 9.4.3 Weighted Random Patterns. 9.4.4 Aliasing. 9.4.5 Some BIST Results. 9.5 Self-Test Applications. 9.5.1 Microprocessor-Based Signature Analysis. 9.5.2 Self-Test Using MISR/Parallel SRSG (STUMPS). 9.5.3 STUMPS in the ES/9000 System. 9.5.4 STUMPS in the S/390 Microprocessor. 9.5.5 The Macrolan Chip. 9.5.6 Partial BIST. 9.6 Remote Test. 9.6.1 The Test Controller. 9.6.2 The Desktop Management Interface. 9.7 Black-Box Testing. 9.7.1 The Ordering Relation. 9.7.2 The Microprocessor Matrix. 9.7.3 Graph Methods. 9.8 Fault Tolerance. 9.8.1 Performance Monitoring. 9.8.2 Self-Checking Circuits. 9.8.3 Burst Error Correction. 9.8.4 Triple Modular Redundancy. 9.8.5 Software Implemented Fault Tolerance. 9.9 Summary. Problems. References. 10 Memory Test. 10.1 Introduction. 10.2 Semiconductor Memory Organization. 10.3 Memory Test Patterns. 10.4 Memory Faults. 10.5 Memory Self-Test. 10.5.1 A GALPAT Implementation. 10.5.2 The 9N and 13N Algorithms. 10.5.3 Self-Test for BIST. 10.5.4 Parallel Test for Memories. 10.5.5 Weak Read-Write. 10.6 Repairable Memories. 10.7 Error Correcting Codes. 10.7.1 Vector Spaces. 10.7.2 The Hamming Codes. 10.7.3 ECC Implementation. 10.7.4 Reliability Improvements. 10.7.5 Iterated Codes. 10.8 Summary. Problems. References. 11 IDDQ. 11.1 Introduction. 11.2 Background. 11.3 Selecting Vectors. 11.3.1 Toggle Count. 11.3.2 The Quietest Method. 11.4 Choosing a Threshold. 11.5 Measuring Current. 11.6 IDDQ Versus Burn-In. 1.7 Problems with Large Circuits. 11.8 Summary. Problems. References. 12 Behavioral Test and Verification. 12.1 Introduction. 12.2 Design Verification: An Overview. 12.3 Simulation. 12.3.1 Performance Enhancements. 12.3.2 HDL Extensions and C++. 12.3.3 Co-design and Co-verification. 12.4 Measuring Simulation Thoroughness. 12.4.1 Coverage Evaluation. 12.4.2 Design Error Modeling. 12.5 Random Stimulus Generation. 12.6 The Behavioral ATPG. 12.6.1 Overview. 12.6.2 The RTL Circuit Image. 12.6.3 The Library of Parameterized Modules. 12.6.4 Some Basic Behavioral Processing Algorithms. 12.7 The Sequential Circuit Test Search System (SCIRTSS). 12.7.1 A State Traversal Problem. 12.7.2 The Petri Net. 12.8 The Test Design Expert. 12.8.1 An Overview of TDX. 12.8.2 DEPOT. 12.8.3 The Fault Simulator. 12.8.4 Building Goal Trees. 12.8.5 Sequential Conflicts in Goal Trees. 12.8.6 Goal Processing for a Microprocessor. 12.8.7 Bidirectional Goal Search. 12.8.8 Constraint Propagation. 12.8.9 Pitfalls When Building Goal Trees. 12.8.10 MaxGoal Versus MinGoal. 12.8.11 Functional Walk. 12.8.12 Learn Mode. 12.8.13 DFT in TDX. 12.9 Design Verification. 12.9.1 Formal Verification. 12.9.2 Theorem Proving. 12.9.3 Equivalence Checking. 12.9.4 Model Checking. 12.9.5 Symbolic Simulation. 12.10Summary. Problems. References. Index.

Scan chain design for test time reduction in core-based ICs

Abstract: The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test application time and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector set for a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pins to embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number of scan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-based ICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC. Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varying design parameters.