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Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.


Papers
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Journal ArticleDOI
M. Soma1, S.D. Huynh, J. Zhang, S. Kim, G. Devarayanadurg 
TL;DR: This article presents an algorithm based on controllability and observability computation for hierarchical analog ATPG that has been implemented in a prototype tool, and results based on several case studies show the application of the technique.
Abstract: Automatic test-pattern generation (ATPG) algorithms for analog circuits have been under intense investigation for the last several years As system design aggressively moves to system-on-a-chip (SoC) and core-based integration, hierarchical analog ATPG emerges as an even more difficult challenge Attempts to develop an effective algorithm have had varying degrees of success This article reviews some fundamental issues and recent work in hierarchical analog ATPG and presents an algorithm based on controllability and observability computation This algorithm has been implemented in a prototype tool, and results based on several case studies show the application of the technique

55 citations

Journal ArticleDOI
TL;DR: It is shown that controllability and observability are indeed resolved if and only if the test system respects timing constraints, even when the system under test is non-real-time.
Abstract: This paper deals with testing distributed software systems. In the past, two important problems have been determined for executing tests using a distributed test architecture: controllability and observability problems. A coordinated test method has subsequently been proposed to solve these two problems. In the present article: 1) we show that controllability and observability are indeed resolved if and only if the test system respects timing constraints, even when the system under test is non-real-time; 2) we determine these timing constraints; 3) we determine other timing constraints which optimize the duration of test execution; 4) we show that the communication medium used by the test system does not necessarily have to be FIFO; and 5) we show that the centralized test method can be considered just as a particular case of the proposed coordinated test method.

54 citations

Proceedings ArticleDOI
30 Apr 2000
TL;DR: The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable and thus need not be tested.
Abstract: This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructions simply because no instruction sequence can produce the desired test sequence which can sensitize the paths and capture the fault effect into the destination output/flip-flop at-speed. These paths are called functionally untestable paths. We discuss the impact of delay defects on the functionally untestable paths on the overall circuit performance and illustrate that they do not need to be tested if the delay defect does not cause the path delay to exceed twice the clock period. Identification of such paths helps determine the achievable path delay fault coverage and reduce the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable and thus need not be tested.

54 citations

Proceedings ArticleDOI
26 Oct 2004
TL;DR: A new transition fault model called as late as possible transition fault (ALAPTF) model, which is capable of detecting smaller gate delays and produces better results in case of process variations is presented.
Abstract: The work presents a new transition fault model called as late as possible transition fault (ALAPTF) model. The model aims at detecting smaller delays, which be missed by both the traditional transition fault model and the path delay model. The model makes sure that each transition is launched as late as possible at the fault site, accumulating the small delay defects along its way. Because some transition faults may require multiple paths to be launched, the simple path-delay model miss such faults. Results on ISCAS'85 and ISCAS'89 benchmark circuits shows that for all the cases, the new model is capable of detecting smaller gate delays and produces better results in case of process variations. For all circuits, on an average, 30% of the time the transition reaches later than traditional models. The algorithm proposed also detects robust and non-robust paths along with the transition faults and the execution time is linear to the circuit size.

54 citations

Journal ArticleDOI
TL;DR: A method for the derivation of fault signatures for the detection of faults in single-output combinational networks is described, which uses the arithmetic spectrum instead of the Rademacher-Walsh spectrum as a form of data compression to reduce the volume of response data at test time.
Abstract: A method for the derivation of fault signatures for the detection of faults in single-output combinational networks is described. The approach uses the arithmetic spectrum instead of the Rademacher-Walsh spectrum. It is a form of data compression that serves to reduce the volume of the response data at test time. The price which is paid for the reduction in the storage requirements is that some of the knowledge of exact fault location is lost. The derived signatures are short and easily tested using very simple test equipment. The test circuitry could be included on the chip since the overhead involved is comparatively small. The test procedure requires a high-speed counter cycling at maximum speed through selected subsets of all input combinations. Hence, the network under test is exercised at speed, and a number of dynamic errors that are not testable by means of conventional test-set approaches will be detected. >

54 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202338
202278
202125
202048
201980
201869