Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Case study: Detecting hardware Trojans in third-party digital IP cores

Abstract: The intellectual property (IP) blocks are designed by hundreds of IP vendors distributed across the world. Such IPs cannot be assumed trusted as hardware Trojans can be maliciously inserted into them and could be used in military, financial and other critical applications. It is extremely difficult to detect Trojans in third-party IPs (3PIPs) simply with conventional verification methods as well as methods developed for detecting Trojans in fabricated ICs. This paper first discusses the difficulties to detect Trojans in 3PIPs. Then a complementary flow is presented to verify the presence of Trojans in 3PIPs by identifying suspicious signals (SS) with formal verification, coverage analysis, removing redundant circuit, sequential automatic test pattern generation (ATPG), and equivalence theorems. Experimental results, shown in the paper for detecting many Trojans inserted into RS232 circuit, demonstrate the efficiency of the flow.

Test generation for sequential circuits

Abstract: An approach to test-pattern generation for synchronous sequential circuits is presented. The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits. Tests for finite-state machines with a large number of states have been successfully generated using reasonable amounts of CPU time and close-to-maximum possible fault coverages have been obtained. For very large sequential circuits, an incomplete scan-design approach to test generation has been developed. The deterministic test generation algorithm is again used to generate test for faults in the modified circuit. All irredundant faults can be detected as in the complete scan design case, but at significantly less area and performance cost. The length of the test sequences for the faults can be bounded by a prescribed value-in general, a tradeoff exists between the number of memory elements required to be made scannable and the maximum allowed length of the test sequence. >

Effect of test set minimization on fault detection effectiveness

Abstract: Given a test set T to test a program P, there are at least two attributes of T that determine its fault detection effectiveness. One attribute is the size of T measured as the number of test cases in T. Another attribute is the code coverage measured when P is executed on all elements of T. The fault detection effectiveness of T is the ratio of the number of faults guaranteed to result in program failure when P is executed on T to the total number of faults present in P. An empirical study was conducted to determine the relative importance of the size and coverage attributes in affecting the fault detection effectiveness of a randomly selected test set for some program P. Results from this study indicate that as the size of a test set is reduced, while the code coverage is kept constant, there is little or no reduction in the fault detection effectiveness of the new test set so generated. For the study reported, of the two attributes mentioned above, the code coverage attribute of a test set is more important than its size attribute. © 1998 John Wiley & Sons, Ltd.

Concurrent simulation of nearly identical digital networks

Abstract: Test patterns for testing digital circuits are usually checked on a test verification program to determine if all or most of the possible faults will be detected. Historically, such a test verification program would be accomplished with many simulations: one for each possible fault.

Generating test cases from UML activity diagram based on Gray-box method

Abstract: Test case generation is the most important part of the testing efforts, the automation of specification based test case generation needs formal or semi-formal specifications. As a semi-formal modelling language, UML is widely used to describe analysis and design specifications by both academia and industry, thus UML models become the sources of test generation naturally. Test cases are usually generated from the requirement or the code while the design is seldom concerned, this paper proposes an approach to generate test cases directly from UML activity diagram using Gray-box method, where the design is reused to avoid the cost of test model creation. In this approach, test scenarios are directly derived from the activity diagram modelling an operation. Then all the information for test case generation, i.e. input/output sequence and parameters, the constraint conditions and expected object method sequence, is extracted from each test scenario. At last, the possible values of all the input/output parameters could be generated by applying category-partition method, and test suite could be systematically generated to find the inconsistency between the implementation and the design. A prototype tool named UMLTGF has been developed to support the above process.