Topic
Automatic test pattern generation
About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.
Papers published on a yearly basis
Papers
More filters
TL;DR: A novel approach to analog circuit fault simulation and test generation is presented by mapping the good and faulty circuits to therete Z-domain and an efficient fault simulation is performed on this discretized circuit for the given input test wave form.
Abstract: Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Zdomain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.
49 citations
TL;DR: X compact is summarized which addresses how unknowns the bane of compression and logic BIST techniques are eliminated, thereby tolerating thousands of Xs and reducing test response data volume by 50 to 2,000 times relative to traditional scan.
Abstract: Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fewer bits. This article summarizes one such method, X compact which addresses how unknowns the bane of compression and logic BIST techniques are eliminated. DFT engineers must spend serious effort to minimize Xs in future designs. It is impossible to eliminate all Xs. X-tolerant response compactors are necessary for tolerating residual Xs to enable massive compaction with practically no impact on test quality. X-compactors are mainly useful for test compression purposes and provide up to 80 times the test response compaction of traditional scan. X-tolerant signature analyzers extend the X-compact concept to incorporate time compaction, thereby tolerating thousands of Xs and reducing test response data volume by 50 to 2,000 times relative to traditional scan. These signature analyzers are extremely beneficial for BIST because Xs can easily corrupt traditional MISR-based BIST signature analyzers. X-tolerant response compactors also enable efficient diagnosis essential to fast yield-learning.
49 citations
TL;DR: A new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD), is proposed and two new TVD basedstatic compaction algorithms are presented.
Abstract: Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and memory requirements for the tester. In this article, a new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD), is proposed. In addition, two new TVD based static compaction algorithms are presented. Experimental results for benchmark circuits demonstrate the effectiveness of the two new static compaction algorithms.
49 citations
13 Mar 2001
TL;DR: A new test generation procedure for sequential circuits using spectral techniques is presented, showing that very high fault coverages and small vector sets are consistently obtained in short execution times for sequential benchmark circuits.
Abstract: We present a new test generation procedure for sequential circuits using spectral techniques. Iterative processes of filtering via compaction and spectral analysis of the filtered test set are performed for each primary input, extracting inherent spectral information embedded within the test sequence. This information, when viewed in the frequency domain, reveals the characteristics of the input spectrum. The filtered and analyzed set of vectors is then used to predict and generate future vectors. We also developed a fault-dropping technique to speed up the process. We show that very high fault coverages and small vector sets are consistently obtained in short execution times for sequential benchmark circuits.
49 citations
TL;DR: It is shown that reasonable predictions are possible for functional tests, but that scan tests, due to misuse of theoretical equations, produce significantly worse quality levels than predicted.
Abstract: The use of stuck-at-fault coverage for estimating overall quality levels is examined. Data from a part tested with both functional and scan tests are analyzed and compared with quality predictions generated by three existing theoretical models. It is shown that reasonable predictions are possible for functional tests, but that scan tests, due to misuse of theoretical equations, produce significantly worse quality levels than predicted. >
49 citations