Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Circularscan: a scan architecture for test cost reduction

Abstract: Scan-based designs are widely used to decrease the complexity of the test generation process; nonetheless, they increase test time and volume. A new scan architecture is proposed to reduce test time and volume while retaining the original scan input count. The proposed architecture allows the use of the captured response as a template for the next pattern with only the necessary bits of the captured response being updated while observing the full captured response. The theoretical and experimental analysis promises a substantial reduction in test cost for large circuits.

Multiple fault diagnosis using n-detection tests

Abstract: We study the relationship between multiple fault diagnosability and fault detection count. Instead of developing a complex diagnostic algorithm for multiple fault behavior, we change the test sets used in test and diagnosis. This allows us to apply a simple single-fault based diagnostic algorithm, and yet achieve very good diagnosability for the failure test cases caused by multiple faults. We have verified experimentally the effectiveness of n-detection tests for multiple-fault cases and explained the results in probabilistic terms.

Method and apparatus for generating transaction-based stimulus for simulation of VLSI circuits using event coverage analysis

Abstract: The present invention applies genetic algorithmic generation of test cases the simulation of VLSI logic circuit blocks. The present invention generates a number of original test cases. This aggregate of solutions is provided to a circuit simulator. The results of the simulator are maintained in a matrix or table. The results detail the number of times that particular logic states or events associated with the VLSI block have been stimulated by particular test cases. The aggregate of solutions and the simulation results are then analyzed by the genetic algorithm. The genetic algorithm preferably identifies states associated with the circuit simulation that have not been produced by the original test cases. The genetic algorithm then combines characteristics of various test cases to generate new test cases. The new test cases are provided to the circuit simulator thereby providing a higher degree of confidence that the entire VLSI chip design has been simulated.

AQUILA: an equivalence checking system for large sequential designs

Abstract: In this paper, we present a practical method for verifying the functional equivalence of two synchronous sequential designs. This tool is based on our earlier framework that uses Automatic Test Pattern Generation (ATPG) techniques for verification. By exploring the structural similarity between the two designs under verification, the complexity can be reduced substantially. We enhance our framework by three innovative features. First, we develop a local BDD-based technique which constructs Binary Decision Diagram (BDD) in terms of some internal signals, for identifying equivalent signal pairs. Second, we incorporate a technique called partial justification to explore not only combinational similarity, but also sequential similarity. This is particularly important when the two designs have a different number of flip-flops. Third, we extend our gate-to-gate equivalence checker for RTL-to-gate verification. Two major issues are considered in this extension: (1) how to model and utilize the external don't care information for verification; and (2) how to extract a subset of unreachable states to speed up the verification process. Compared with existing approaches based on symbolic Finite State Machine (FSM) traversal techniques, our approach is less vulnerable to the memory explosion problem and, therefore, is more suitable for a lot of real-life designs. Experimental results of verifying designs with hundreds of flip-flops will be presented to demonstrate the effectiveness of this approach.

Exact evaluation of diagnostic test resolution

Abstract: The authors introduce a new measure of the diagnostic resolution of a test set: the sizes of all equivalence classes in the circuit under the test set. This measure is a better indicator of the diagnostic capabilities of a test set than single-value metrics based on undistinguished pairs of faults or completely distinguished faults. A symbolic algorithm for computing equivalence class sizes has been used to evaluate the diagnostic resolution of deterministic single-stuck-at fault test sets for ISCAS combinational and sequential benchmark circuits. >