Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Method and apparatus for bus executed boundary scanning

Abstract: A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transfer test data into the integrated circuit under boundary scan test, and uses the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor of the system.

Experimental Evaluation of Testability Measures for Test Generation

Abstract: This paper presents results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms. Each measure was evaluated using over 60 000 faults in circuits of varying size and complexity. The per- formance of these measures was rated using several different criteria. Based on these results the performance of a composite test generation strategy that uses multiple guidance heuristics was evaluated. The re- sults indicate that this strategy not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable.

Pseudofunctional testing

Abstract: Recent research results have shown that the traditional structural testing for delay and signal integrity faults may result in overtesting due to the nontrivial number of such faults that are untestable in the functional mode although testable in the test mode. This paper presents a pseudofunctional-test methodology that attempts to minimize the overtesting problem of the scan-based circuits in automatic test pattern generation (ATPG) and built-in self-test (BIST) test generation approaches. The first pattern of a two-pattern test is still delivered by scan in the test mode but the pattern is generated in such a way that it does not violate the functional constraints extracted from the functional logic. The second pattern is then generated in a functional mode using the functional justification (also called broadside) test application scheme. The authors use a sequential boolean satisfiability solver to extract a set of functional constraints that consists of illegal states and internal signal correlation. The functional constraints are imposed upon an ATPG tool to generate pseudofunctional tests and/or implemented as a monitor in the BIST environment to allow only functional-like patterns generated from the random test pattern generator as tests. The experimental results for delay faults indicate that the percentage of functionally untestable delay faults is nontrivial for many circuits. This finding supports the hypothesis of the overtesting problem in delay testing. In addition, the results indicate the effectiveness of the proposed constraint extraction method and the proposed BIST scheme.

Enhancing high-level control-flow for improved testability

Abstract: In this study, we present a controllability measure for high-level circuit descriptions and a high-level synthesis-for-testability technique. Unlike many recent studies in the area of high-level synthesis for testability that focus on improving the testability of data paths, the objective of our approach is to improve the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, a shorter ATPG time, a smaller test set, and better fault coverage and ATPG efficiency are often achieved. Implementation of this technique requires minimal logic and performance overheads and allows test vectors to be applied at clock-speed.

Diagnostic Test Generation for Arbitrary Faults

Abstract: It is now generally accepted that the stuck-at fault model is no longer sufficient for many manufacturing test activities. Consequently, diagnostic test pattern generation based solely on distinguishing stuck-at faults is unlikely to achieve the resolution required for emerging fault types. In this work we describe a new diagnostic ATPG implementation that uses a generalized fault model. It can be easily used in any diagnosis framework to refine diagnostic resolution for complex defects. For various types of faults that include, for example, bridge, transition, and transistor stuck-open, we show that diagnostic resolution can be significantly enhanced over a traditional diagnostic test set aimed only at stuck-at faults. Finally, we illustrate the use of our diagnostic ATPG to distinguish faults derived from a state-of-the-art diagnosis flow based on layout.