Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Do Automatically Generated Unit Tests Find Real Faults? An Empirical Study of Effectiveness and Challenges (T)

Abstract: Rather than tediously writing unit tests manually, tools can be used to generate them automatically --- sometimes even resulting in higher code coverage than manual testing. But how good are these tests at actually finding faults? To answer this question, we applied three state-of-the-art unit test generation tools for Java (Randoop, EvoSuite, and Agitar) to the 357 real faults in the Defects4J dataset and investigated how well the generated test suites perform at detecting these faults. Although the automatically generated test suites detected 55.7% of the faults overall, only 19.9% of all the individual test suites detected a fault. By studying the effectiveness and problems of the individual tools and the tests they generate, we derive insights to support the development of automated unit test generators that achieve a higher fault detection rate. These insights include 1) improving the obtained code coverage so that faulty statements are executed in the first instance, 2) improving the propagation of faulty program states to an observable output, coupled with the generation of more sensitive assertions, and 3) improving the simulation of the execution environment to detect faults that are dependent on external factors such as date and time.

Fault modeling and test algorithm development for static random access memories

Abstract: A fault model for SRAMs (static random-access memories) is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms (length 9N and 13N respectively, where N is the number of addresses) plus a data retention test are proposed that cover 100% of the faults under the fault model. The 13N test algorithm is generally applicable while the 9N algorithm can only be used in SRAMs with combinational R/W logic. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms is verified by a large number of actual wafer tests and device failure analysis. >

Method for manufacturing test simulation in electronic circuit design

Abstract: A manufacturing and test simulation method for electronic circuit design integrated with computer aided design tools to provide concurrent engineering of manufacturing and testability aspects of a product concurrent with the functional design of a product. The manufacturing and test simulator (MTSIM) simulates manufacturing test and repair aspects of boards and multichip modules (MCMs) from design concept through manufacturing release to aid the designer in selecting appropriate trade-offs in the design for manufacturability and the design for testability. All simulation by the methods of the present invention applies manufacturing and test models down to the component level. The methods of the simulator include a new yield model for boards and MCMs which accounts for the clustering of solder defects. MTSIM models solder faults, manufacturing workmanship faults, component performance faults, and reliability faults. Fault probabilities for the circuit design are estimated based on the component type, the component functionality, and the assembly process used. Up to seven manufacturing test steps can be simulated by MTSIM. Test coverage models will support all commonly used manufacturing test methodologies, including visual inspection, in-circuit test, IEEE 1149.1 boundary scan, selftest, diagnostics, and burn-in. Pareto and iterative "what-if" analysis may be used to locate particular enhancements which most benefit the manufacturability and testability of the product.

Software-based self-testing of embedded processors

Abstract: Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.

Design for testability using scanpath techniques for path-delay test and measurement

Abstract: 1. Abstract This paper describes a novel flip-flop design which is used in performing internal path-delay test and measurement using scanpath technique:;. Also described is the design for a boundary-scan cell that enables inpUtlOUtpUt delays to be measured. The paper includes a real-life application example.