Topic
Automatic test pattern generation
About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.
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16 Aug 2000TL;DR: In this paper, a technique for detecting defects such as short circuits in a device, such as a discrete pixel detector used in a digital x-ray system, is described, which employs test circuits (122, 124, 126) associated with each row driver.
Abstract: A technique is described for detecting defects such as short circuits in a device
such as a discrete pixel detector used in a digital x-ray system (10). The
technique employs test circuits (122, 124, 126) associated with each row driver (46)
of the detector. The test circuits are enabled by a test enable signal (150), and the row
driver sequentially enables the rows of the detector, along with the individual test
circuits. In a test sequence, output signals from the two test circuits are
monitored to identify whether a defect, such as a short circuit, is likely to exist in the
row or row driver. The test circuitry adds only minimal area and complexity to the
row driver function, providing a high degree of test coverage at a low cost, with
minimal likelihood of test circuitry-induced failures.
47 citations
01 May 2005
TL;DR: The J-scan shifts two bits of scan data per clock cycle so the scan clock frequency is halved without increasing the test time, reducing the test power by two thirds compared with the traditional MUX scan.
Abstract: This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan clock frequency is halved without increasing the test time. The experimental data show that the proposed technique effectively reduces the test power by two thirds compared with the traditional MUX scan. The presented technique requires very few changes in the existing MUX-scan design for testability methodology and needs no extra computation. The penalties are area overhead and speed degradation.
47 citations
TL;DR: It is shown that with low test area and test data overhead substantial savings in power dissipation during test application are achieved in very low computational time for both small and large test sets.
Abstract: The paper presents a novel technique for power minimization during test application in sequential circuits using multiple scan chains. The technique is based on a new design for test architecture and a novel test application strategy which reduces spurious transitions in the circuit under test. To facilitate the reduction of spurious transitions, the proposed design for test architecture is based on classifying scan latches into compatible, incompatible and independent scan latches. Based on their classification, the scan latches are partitioned into multiple scan chains and a single extra test vector associated with each scan chain is computed. A new test application strategy which applies the extra test vector to primary inputs while shifting out test responses for each scan chain, minimizes power dissipation by eliminating the spurious transitions which occur in the combinational part of the circuit. The newly introduced multiple scan chain-based technique does not introduce performance degradation and minimizes clock tree power dissipation with minimal impact on both test area and test data overhead. Unlike previous approaches which are test set dependent, and hence are not able to handle large circuits due to the complexity of the design space, the paper shows that with low test area and test data overhead substantial savings in power dissipation during test application are achieved in very low computational time for both small and large test sets. For example, in the case of the benchmark circuit s15850, it takes <6009 in computational time and <1 percent in test area and test data overhead to achieve over 80 percent savings in power dissipation.
47 citations
11 May 2005
TL;DR: An efficient ATPG algorithm that makes use of powerful SAT-solving techniques and can also cope with tri-states is presented.
Abstract: Automatic test pattern generation (ATPG) based on Boolean satisfiability (SAT) has been proposed as an alternative to classical search algorithms. SAT-based ATPG turned out to be more robust and more effective by formulating the problem as a set of equations. In this paper, we present an efficient ATPG algorithm that makes use of powerful SAT-solving techniques. Problem specific heuristics are applied to guide the search. In contrast to previous SAT-based algorithms, the new approach can also cope with tri-states. The algorithm has been implemented as the tool PASSAT. Experimental results on large industrial circuits are given to demonstrate the quality and efficiency of the algorithm.
47 citations
TL;DR: In this paper, the feasibility of a qualitative approach for detecting faults in an air conditioning system is considered, where the system considered is a multi-zone variable air volume air-handling unit, and the faults investigated include types which result in deterioration of operation, as distinct from actual failure.
Abstract: The feasibility of a qualitative approach for detecting faults in an air-conditioning system is considered. The system considered is a multi-zone variable air volume air-handling unit, and the faults investigated include types which result in deterioration of operation, as distinct from actual failure. The operating modes of the sequential controller for the central air-handling plant can be matched to a corresponding qualitative classification of steady-state temperatures. Observed mismatches indicate the presence of faults. Trials of the method in an air-conditioning test laboratory are reported. >
47 citations