Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Analyzing Fault Models for Reversible Logic Circuits

Abstract: Reversible logic computing is a rapidly developing research area. Testing such circuits is obviously an important issue. In this paper, we consider a new fault model, labeled crosspoint faults, for reversible logic circuits. A randomized Automatic Test Pattern Generation algorithm targeting this specific kind of fault is introduced and analyzed. Simulation results show that the algorithm yields very good performance. The relationship between the crosspoint faults and stuck-at faults is also investigated. We show that the crosspoint fault model is a better fault model for reversible circuits since it dominates the traditional stuck-at fault model in most instances.

Fault diagnostic system incorporating behavior models

Abstract: A fault diagnostic system for a unit under test is disclosed which features behavior models for incorporating design knowledge of the unit under test into the system so as to implement a specification-based diagnostic approach while reducing the number of diagnostic tests. The arrangement is such that the featured diagnostic capabilities can be used with automatic test equipment or test instrumentation, and may be used to provide test programs for the automatic test equipment.

Method for automatically generating test vectors for digital integrated circuits

Abstract: A sequential circuit test generation system and method to generate test patterns for sequential without assuming the use of scan techniques or a reset state utilizes the iterative logic array (ILA) model of the sequential circuit and a targeted-D propagation scheme employing both forward time processing (FTP) and reverse time processing (RTP) techniques for assigning a sequence of primary input (PI) values and for producing a an initial pseudo primary input (PPI) vector representing the initial state of the digital circuit at a particular time frame Improved state justification techniques generate the remaining sequence of PI vectors necessary to put the circuit into the initial state from either known or don't care first states, by means of a heuristic method for reducing required initial state assignments The method can also be applied to reduce the required number of PI vector assignments is also presented In another phase of test vector generation, knowledge about the digital circuit behavior is obtained from a fault simulator to identify circuit nodes at which error signals are activated and partly propagated by already generated sequences of test vectors, and this knowledge is utilized with FTP techniques to generate test vector sequences for these nodes

Electronic test program that can distinguish results

Abstract: An electronic test system that distinguishes erroneous and marginal results. The test system includes a memory and an electronic processor for controlling the execution of the test, obtaining test results and generating test results. The test results include a determination of whether the condition of the test datapoints is pass, fail, error or marginal, where pass indicates that the DUT has met a specification, fail indicates that the DUT has not met the specification, error indicates that the test system or interface to the DUT has failed, and marginal indicates that the system is marginally within specification. The test results are displayed on a graphical user interface. The test system provides the ability to control the progress of the test system based on the results. For example, the system can be programmed to stop on erroneous results, marginal results, failed results, combinations of the forgoing, or stop after each measurement. When the system stops, a drop-down window appears explaining the reason for the stoppage.

Verification algorithms for VLSI synthesis

Abstract: A description is given of a theory for, and the application of, a general algorithm for determining whether a given multilevel Boolean function is a tautology or whether two given multilevel Boolean functions are equivalent. Four specific cases of this general algorithm are examined. These are termed the flattening method, the don't-care method, the simulation method, and the algebraic string comparison method. A single unifying algorithm frame is given for the implementation of any of these four methods, depending on parameterization. Experimental results are given which indicate that, with the exception of the don't-care method, each of these methods has a problem class in which it is clearly superior to the others. The primary application of these algorithms is as a verification tool for silicon compilation systems. However, these algorithms are also being used as the foundation for multilevel logic minimization and automatic test pattern generation programs. >