Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

A hybrid coding strategy for optimized test data compression

Abstract: Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that run-length coding, particularly alternating run-length coding, can provide high compression ratios for the test data. However, experimental data show that longer runlengths are distributed sparsely in the code space and often occur only once, which implies an ineficient encoding. In this study a hybrid encoding strategy is presented which overcomes this problem by combining both the advantages of run-length and dictionary-based encoding. The compression ratios strongly depend on the strategy of mapping don't cares in the original test set to zeros or ones. To find the best assignment an algorithm is proposed which minimizes the total size of the test data consisting of the encoded test set and the dictionary. Experimental results show that the proposed approach works particularly well for larger examples yielding a significant reduction of the total test data storage compared to pure alternating run-length coding.

Efficient identification of (critical) testable path delay faults using decision diagrams

Abstract: We present a novel framework to identify all the testable and untestable path delay faults (PDFs) in a circuit. The method uses a combination of decision diagrams for manipulating PDFs as well as Boolean functions. The approach benefits from processing partial paths or fanout-free segments in the circuit rather than the entire path. The methodology is modified to identify all testable critical PDFs under the bounded delay fault model. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology outperforms any existing method for identifying testable PDFs. Its scalability by focusing on critical PDFs is demonstrated by experimenting on very path-intensive benchmarks.

Adaptive Alternate Analog Test

Abstract: Adaptive test is a promising approach for test cost reduction. This article presents an adaptive test scheme for analog circuits that capitalizes on alternate test to achieve a low cost for the majority of fabricated devices. The small fraction of devices for which the alternate test decision may be prone to error are identified and further action is taken.

Multiple fault detection using single fault test sets

Abstract: A simulation study of the 74LS181 4-b ALU (arithmetic logic unit) using 16 complete single stuck-at fault test sets demonstrated significantly higher multiple stuck-at fault coverage than predicted by previous theoretical studies. Analysis of the undetected multiple faults shows the effect of circuit and test set characteristics on fault coverage. A fault masking property, defined as self-masking, is observed for the undetected faults in the simulation study. A heuristic is described for evaluating the multiple fault coverage of single stuck-at fault test sets. A second heuristic generates augmented test sets, providing improved multiple stuck-at fault coverage with a minimal increase in test set development cost. >

High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor

Abstract: As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.