Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

An efficient delay test generation system for combinational logic circuits

Abstract: An efficient delay test generation (DTEST GEN) system for combinational logic circuits is presented. In the DTEST GEN system, delay testing problems are divided into gross delay faults and small delay faults separately so that the tradeoff between the levels of delay testing effort and the confidence levels of proper system operation can be explored. Complete automatic test pattern generation (ATPG) algorithms are proposed for both gross delay faults and small delay faults. A novel timing analysis method for delay test generation which uses a conventional depth-first search technique and a novel functionality analysis technique is introduced. The functionality analysis technique examines, necessary conditions for a given delay fault to be testable and estimates the upper bound of the good circuit propagation delay of the longest sensitizable path passing through the fault site. Several benchmark results are demonstrated for both gross delay fault testing and small delay fault testing. >

GARDA: a diagnostic ATPG for large synchronous sequential circuits

Abstract: The paper deals with automated generation of diagnostic test sequences for synchronous sequential circuits. An algorithm is proposed, named GARDA, which is suitable to produce good results with acceptable CPU time and memory requirements even for the largest benchmark circuits. The algorithm is based on Genetic Algorithms, and experimental results are provided which demonstrate the effectiveness of the approach. >

Increasing Scan Compression by Using X-chains

Abstract: Scan testing and scan compression are key to realizing cost reduction and quality control of ever more complex designs. However, compression can be limited if the density of unknown (X) values is high. We present a method to identify a small, but important, subset of scan cells that are "likely" to capture an X, place them on separate "X-chains", create a combinational unload compressor tuned for these X-chains, and modify test generation to take advantage of this circuit. This method is fully integrated in the design-for-test (DFT) flow, requires no additional user input and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.

Probabilistic mixed-model fault diagnosis

Abstract: Previously-proposed strategies for VLSI fault diagnosis have suffered from a variety of self-imposed limitations. Some techniques are limited to a specific fault model, and many will fail in the face of any unmodeled behavior or unexpected data. Others apply ad-hoc or arbitrary scoring mechanisms to fault candidates, making the results difficult to interpret or to compare with the results from other algorithms. This paper outlines an approach to fault diagnosis that is robust, comprehensive, extendable, and practical. By introducing a probabilistic framework for diagnostic prediction, it is designed to incorporate disparate diagnostic algorithms, different sets of data, and a mixture of fault models into a single diagnostic result. Results from diagnosis experiments on a Hewlett-Packard ASIC and FIB inserted defects are presented.

Modeling the economics of testing: a DFT perspective

Abstract: Decision-makers typically make test tradeoffs using models that mainly represent direct costs such as test generation time and tester use. Analyzing a test strategy's impact on other significant factors such as test quality and yield learning requires an understanding of the dynamic nature of the interdomain dependencies of test, manufacturing, and design. Our research centers on modeling the tradeoffs between these domains. To answer the DFT question, we developed the Carnegie Mellon University Test Cost Model, a DFT cost-benefit model, derived inputs to the model for various IC cases with different assumptions about volume, yield, chip size, test attributes, and so forth; and studied DFT's impact on these cases. We used the model to determine the domains for which DFT is beneficial and for which DFT should not be used. The model is a composite of simple cause-and-effect relationships derived from published research. It incorporates many factors affecting test cost, but we don't consider it a complete model. Our purpose is to illustrate the necessity of using such models in assessing the effectiveness of various test strategies.