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Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.


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01 Jan 1990
TL;DR: This dissertation describes a new method for generating test patterns: the Boolean satisfiability method, which is quite general and allows for the addition of any heuristic used by the structural search methods.
Abstract: A combinational circuit can be tested for the presence of a single stuck-at fault by applying a set of inputs that excite a verifiable output response in that circuit. If the fault is present, the output will be different than it would be if the fault were not present. Given a circuit, the goal of an automatic test pattern generating system is to generate a set of input sets that will detect every possible single stuck-at fault in the circuit. This dissertation describes a new method for generating test patterns: the Boolean satisfiability method. The new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits. Second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from most programs now in use, which directly search the circuit data structure instead of constructing a formula from it. The new method is quite general and allows for the addition of any heuristic used by the structural search methods. The Boolean satisfiability method has produced excellent results on popular test pattern generation benchmarks.

44 citations

Proceedings ArticleDOI
27 Apr 2008
TL;DR: This work presents the first step in developing an alternative test methodology for scan cell internal faults, and defines a new flush test that is shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault coverage, respectively.
Abstract: Scan chains contain approximately 50% of the logic transistors in large industrial designs. Yet, faults in the scan cells are not directly targeted by scan tests and assumed detected by flush tests. Reported results of targeting the scan cell internal faults using checking sequences show such tests to be about 4.5 times longer than scan stuck-at test sets and require a sequential test generator, even for full scan circuits. We present the first step in developing an alternative test methodology for scan cell internal faults. Fault detection capability of existing tests (flush tests, stuck-at tests and transition delay fault tests) are quantified. Existing tests are shown to have similar coverage as checking sequences. A new flush test, viz. half-speed flush test, is defined. This new test is shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault coverage, respectively.

44 citations

Proceedings ArticleDOI
08 Dec 2008
TL;DR: Experimental results show that interconnect-delay variations can have a significant impact on the long paths that must be targeted for the detection of SDDs, and the proposed pattern-grading and pattern-selection method is more effective than a commercial timing-aware ATPG tool, and requires considerably less CPU time.
Abstract: Timing-related failures in high-performance integrated circuits are being increasingly dominated by small-delay defects (SDDs). Such delay faults are caused by process variations, crosstalk, power-supply noise, and defects such as resistive shorts and opens. Recently, the concept of output deviations has been presented as a surrogate long-path coverage metric for SDDs. However, this approach is focused only on delay variations for logic gates and it ignores chip layout, interconnect defects, and delay variations on interconnects. We present a layout-aware output deviations metric that can easily handle interconnect delay variations. Experimental results show that interconnect-delay variations can have a significant impact on the long paths that must be targeted for the detection of SDDs. For the same pattern count, the proposed pattern-grading and pattern-selection method is more effective than a commercial timing-aware ATPG tool for SDDs, and requires considerably less CPU time.

44 citations

Book ChapterDOI
27 Mar 2006
TL;DR: In this article, the authors present a theory and technique for generating fault-based test cases for concurrent systems, based on the notion of refinement, which is used to generate test purposes from faults that have been injected into a model of the system under test, which form a specification of a more detailed test case that can detect the injected fault.
Abstract: Fault-based testing is a technique where testers anticipate errors in a system under test in order to assess or generate test cases. The idea is to have enough test cases capable of detecting these anticipated errors. This paper presents a theory and technique for generating fault-based test cases for concurrent systems. The novel idea is to generate test purposes from faults that have been injected into a model of the system under test. Such test purposes form a specification of a more detailed test case that can detect the injected fault. The theory is based on the notion of refinement. The technique is automated using the TGV test case generator and an equivalence checker of the CADP tools. A case study of testing web servers demonstrates the practicability of the approach.

44 citations

Proceedings ArticleDOI
03 Mar 2003
TL;DR: This work presents a novel success-driven learning algorithm which significantly accelerates an ATPG engine for enumerating all solutions (preimages) and effectively prunes redundant search space due to overlapped solutions and constructs a free BDD on the fly so that it becomes the representation of the preimage set at the end.
Abstract: Preimage computation is a key step in formal verification. Pure OBDD-based symbolic method is vulnerable to the space-explosion problem. On the other hand, conventional ATPG/SAT-based method can handle large designs but can suffer from time explosion. Unlike methods that combine ATPG/SAT and OBDD, we present a novel success-driven learning algorithm which significantly accelerates an ATPG engine for enumerating all solutions (preimages). The algorithm effectively prunes redundant search space due to overlapped solutions and constructs a free BDD on the fly so that it becomes the representation of the preimage set at the end. Experimental results have demonstrated the effectiveness of the approach, in which we are able to compute preimages for large sequential circuits, where OBDD-based methods fail.

44 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202338
202278
202125
202048
201980
201869