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Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.


Papers
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Journal ArticleDOI
TL;DR: The effectiveness of a random built-in self-test technique for VLSI circuits is studied and simple formulas are developed, which give very accurate estimations without detailed circuit simulation.
Abstract: The effectiveness of a random built-in self-test technique for VLSI circuits is studied. This technique, called the circular self-test path (CSTP), is applicable to circuits that consist of combinational blocks and registers. In particular, the effectiveness of test pattern generation, the effectiveness of test response compaction and fault coverage are examined. The test generation effectiveness is evaluated by the fraction of all possible test patterns applied during a testing session to the circuit under test. The compaction effectiveness of the CSTP technique is measured by the probability of aliasing, and fault coverage by the fraction of all permanent faults that are detected. For all these measures, simple formulas are developed, which give very accurate estimations without detailed circuit simulation. To demonstrate their accuracy, the estimates obtained by the formulas are compared to the results obtained by extensive simulation experiments. >

43 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR) together with the dynamic compaction algorithm, called MinTest.
Abstract: This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR). These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. The test sets generated by MinTest are 30% smaller than the previously published two-pattern test set compaction results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits.

43 citations

Book ChapterDOI
01 Jan 1998
TL;DR: This work is studying possibilities to test software using genetic algorithm search to produce test cases in order to find problematic situations like processing time extremes using automated dynamic stress testing.
Abstract: In this work we axe studying possibilities to test software using genetic algorithm search. The idea is to produce test cases in order to find problematic situations like processing time extremes. The proposed test method comes under the heading of automated dynamic stress testing.

43 citations

Proceedings ArticleDOI
03 Nov 1997
TL;DR: A methodology for performing defect localization based upon IDDq test information (only) is presented, which supports multiple fault models and has been successfully applied to a large number of samples-including ones that have been verified through failure analysis.
Abstract: A current disadvantage of IDDq testing is lack of software-based diagnostic tools that enable IC vendors to create a large database of defects uniquely detected with this test method. We present a methodology for performing defect localization based upon IDDq test information (only). Using this technique, fault localization can be completed within minutes (e.g. <5 minutes) after IC testing is complete. This technique supports multiple fault models and has been successfully applied to a large number of samples-including ones that have been verified through failure analysis. Data is presented related to key issues such as diagnostic resolution, hardware-to-fault model correlation, diagnostic current thresholds, and the diagnosability of various defect types.

43 citations

Proceedings ArticleDOI
01 Jan 1999
TL;DR: A procedure for application-dependent self testing of an in-circuit reprogrammable FPGA is proposed and BIST schemes that preserve theFPGA timing are developed and compared with reported BIST techniques that rely on the design of test pattern generators best suited for pseudoexhaustive testing of delay faults.
Abstract: To ensure correct operation of an FPGA based system with regard to timing characteristics, an application-dependent FPGA testing, i.e. testing of an FPGA programmed to implement a user-defined function, must be performed. We propose a procedure for application-dependent self testing of an in-circuit reprogrammable FPGA and develop BIST schemes that preserve the FPGA timing. For these schemes, the reconfiguration of a portion of the FPGA into test resources has no impact on the timing characteristics of that part of the FPGA which is currently being tested. We also present a method for enhancing the susceptibility of FPGA delay faults to random testing. It is based on modifying the functions of programmable logic components in the section under test. We compare the efficiency of the self-test scheme that uses this method with the earlier reported BIST techniques that rely on the design of test pattern generators best suited for pseudoexhaustive testing of delay faults.

43 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202338
202278
202125
202048
201980
201869