Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Physical failures and fault models of CMOS circuits

Abstract: As CMOS has emerged as an important technology for VLSI, testing of large CMOS networks has become a crucial issue. This paper considers single physical failures in a CMOS gate and shows their effect in terms of logic faults. The existence of such a correspondence is verified by simulation results, and a transistor-level fault model is given. To make the test process simpler, a comprehensive fault model of CMOS circuits wherein CMOS stuck-open (s-op) faults are transformed into the classical gate-level TTL stuck-at (s-a) faults has been obtained. This transformation makes the testing of CMOS combinational circuits equivalent to the testing of transformed TTL sequential circuits and eliminates any need for special consideration of s-op faults. The superiority of this gate-level model over other models is its ability to be integrated into the cell libraries of existing automatic test pattern generation (ATPG) packages. This model is also useful for multiple faults when either s-a or s-op faults, or both, are present. Several examples are included to illustrate the versatility and usefulness of this gate-level fault model.

A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults

Abstract: Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of each fault site lead to increased test set size and require more tester memory. In this paper we propose a new ATPG algorithm to find a near-minimal test pattern set that detects faults multiple times and achieves excellent defective part level. This greedy approach uses 3-value fault simulation to estimate the potential value of each vector candidate at each stage of ATPG. The result shows generation of a close to minimal vector set is possible only using dynamic compaction techniques in most cases. Finally, a systematic method to trade-off between defective part level and test size is also presented.

Delay-fault diagnosis by critical-path tracing

Abstract: A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented. >

SRAM-Based FPGAs: Testing the Embedded RAM Modules

Abstract: This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called ‘pseudo shift register’ for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called ‘shifted MATS++’ is described.

On compacting test sets by addition and removal of test vectors

Abstract: This paper presents a method of test compaction for stuck-at faults in combinational circuits, that complements previously proposed methods and allows further reduction in test set size in a cost-effective way. A given test set is compacted by generating additional test vectors. Each test vector added allows the removal of two or more test vectors from the existing test set, thus reducing its size. Experimental results for benchmark circuits demonstrate the effectiveness of the method. >