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Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.


Papers
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Proceedings ArticleDOI
Chen Zhang1, Zhenyu Chen1, Zhihong Zhao1, Shali Yan1, Jinyu Zhang1, Baowen Xu1 
14 Jul 2010
TL;DR: This paper presents a new regression test selection technique by clustering the execution profiles of modification-traversing test cases, which can produce a smaller test suite with most fault-revealing test cases in comparison with existing selection techniques.
Abstract: In order to improve the efficiency of regression testing, many test selection techniques have been proposed to extract a small subset from a huge test suite, which can approximate the fault detection capability of the original test suite for the modified code. This paper presents a new regression test selection technique by clustering the execution profiles of modification-traversing test cases. Cluster analysis can group program executions that have similar features, so that program behaviors can be well understood and test cases can be selected in a proper way to reduce the test suite effectively. An experiment with some real programs is designed and implemented. The experiment results show that our approach can produce a smaller test suite with most fault-revealing test cases in comparison with existing selection techniques.

43 citations

Journal ArticleDOI
TL;DR: It is shown that efficient test algorithms can be generated automatically for bit- oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults.
Abstract: The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults.

42 citations

Proceedings ArticleDOI
01 Nov 2010
TL;DR: Two new methodologies to significantly improve the overall defect coverage of cell-internal Bridges over a wide range of Bridge resistor values and the second method concentrates on library cell- internal high-resistive Open defects are presented.
Abstract: Industry is facing very high quality requirements for today's and tomorrow's ICs. Especially in the automotive market these quality requirements need to be fulfilled. To achieve this we need to improve currently used test methods and fault models to improve the overall defect coverage. This paper presents two new methodologies to significantly improve this situation. One method will focus on cell-internal Bridges over a wide range of Bridge resistor values and the second method concentrates on library cell-internal high-resistive Open defects. The fault models used during the ATPG are enhanced to directly target the layout-based intra-cell Open and Bridge defects. Both methods have been evaluated on 1500 library cells of a 65nm technology. In addition the wide range of intracell Bridges has been evaluated on 10 real industrial designs with up to 60 million faults. Various results are presented from all 1500 library cells and from the 10 industrial designs as well.

42 citations

Journal ArticleDOI
Zhuo Li1, Xiang Lu1, Wangqi Qiu1, Weiping Shi1, Duncan M. Walker1 
TL;DR: A physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults is proposed and an accurate yet simple delay calculation method is proposed.
Abstract: Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.

42 citations

Proceedings ArticleDOI
03 Nov 1997
TL;DR: A procedure is described for inserting control points in the UDL to modify its output space so that it contains the specified core test vectors, to avoid performance degradation by keeping test logic off the critical timing paths.
Abstract: Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (UDL) surrounding the core may restrict the set of test vectors that can be applied to the core. Consequently, some of the core test vectors specified by the core supplier may not be contained in the output space of the UDL that drives the core and hence cannot be justified at the core inputs. Conventional solutions to this problem involve placing multiplexers or boundary scan elements at the inputs of the core to provide test access. This can be very costly in terms of area and performance. This paper presents a new approach for providing test access to an embedded core. A procedure is described for inserting control points in the UDL to modify its output space so that it contains the specified core test vectors. The flexibility in selecting the location of the control points is used to avoid performance degradation by keeping test logic off the critical timing paths. Experimental results are shown comparing the control point insertion procedure with other approaches.

42 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202338
202278
202125
202048
201980
201869