Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

On the detection of delay faults

Abstract: The class of faults known as gate delay faults are investigated. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to detect gate delay faults are proposed. A physically meaningful measure to assess the efficacy of test sequences is introduced, and used to report fault coverages. A nine-valued logic system was proposed and used for deriving these tests. A physically meaningful measure, in the form of the average detection size of a test sequence. An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported. >

Impact of multiple-detect test patterns on product quality

Abstract: This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects. Volumedata obtained by testing a production ASIC with these new multiple-detect patterns shows increased defect screening capability and very good agreement with the bridging coverage estimated by the ATPG tool. 1. Introduction One of the key objectives of manufacturing test is to ensure high quality of shipped parts while managing the cost of test. Scan–based DFT methodology, combined with ATPG tools, automate the generation of test patterns with very high fault coverage. The advantage ofa structure-based ATPG tool is its high efficiency and effectiveness in generating a test set by targeting different fault models, such as stuck-at, transition, path delay, and DDQ . DFT tooI ls assess the quality of test patterns by reporting the fault coverage of the target fault models. However, real defects may not always be detected by test patterns generated for the targeted fault model. The stuck-at fault model has been used in DFT ince sthe very beginning and, while showing some limitations and imperfections, it has demonstrated its robustness and adaptability. Even though the stuck-at fault model may not always model behavior of a faulty circuit it serves very well as a target, i.e. a test set developed to test stuck-at faults will also cover many other defects that do not behave as stuck-at faults. Good understanding of bridging defects is at the center of explanation of the effectiveness of the stuck-at fault model. It also provides the key clues to its enhancements. In an experimental study of bridging faults in a state of the art microprocessor design [1] it has been observed that approximately 80% of all bridges occur between a node and Vcc or Vss, and 20% involve nonsupply nod- es. Global signals were involved in 70% of these defects and leaf-level signals contributed only 30%. In another experimental evaluation of scan tests for bridging defects [2] it was concluded that bridges with power rails contributed between 60% to 90% of all bridging defects. It is clear that a test that detect a stuck-at fault on a node willdetect a low resistive bridging defect with the supply lines. This is exactly the behavior of a node stuckat- -0 or stuckat- -1. However, the detection of node-to-node bridging defects is not guaranteed. If a stuckat fault on a node is detected once, the- probability f detecting a static bridging fault witho another un-correlated node that has signal probability 50% is also 50% [3].If the stuck at fault is detected- twice, the estimated probability of detecting the bridging fault with another node acting as an aggressor is 75%. Signal correlation may reduce the coverage of nodeto-node bridging faults. It was- observed [1] that a test set with greater than 95% stuck-at fault coverage produced only 33% coverage of nodeto-node bridging faults. Most likely the- disappointing coverage was an artifact of signal correlation. Typically a test set created by conventional ATPG aiming at single detection may have up to 6% of faults detected only once and up to 10% of faults detected only once or twice. This may result in inadequate coverage of nodeto-node -bridging defects. In general, there are two directions to overcome the limitation and improve the test quality. One direction is to enhance the fault model by describing the defect behavior and presenting it in a suitable form to the ATPG tool. In this case the fault model is more precise and complex and the fault list s longer. Thei advanced fault models, like bridging faults and cross-talk effects, use physical layout information to compile the fault lists. A complete example of this approach is demonstrated in [2]. Here the possible bridges are identified by analysis of layout using weighted critical area and their behavior is modeled by different types of faults and a special netlist. The experimental results from the project show that

An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagat

Abstract: In this paper, we present a fast fault simulator, FSIM, for combinational circuits. FSIM is based on the parallel pattern single fault propagation (PPSFP) technique. The essential idea of FSIM is to simulate the circuit in the forward levelized order and to prune off unnecessary gates in the early stages. In this way, FSIM performs fault simulations only for the gates which are affected by 'the injected faults. Another key feature employed in FSIM is the use of multiple last-in first-out (L,IFO) stacks instead of the commonly used priority queue [9]. The propagation time of the mult,iple LIFO stacks is O(n) and that of the priority queue O(n log n), where n is the number of gates in the propagation zone of the fault under consideration. The two features achieve a substantial reduction of the processing time. Experimental results for ten benchmark circuits show that FSIM outperforms other competing PPSFP fault simulators, Moreover, the efficiency of FSIM is less dependent on the circuit structure than other fault simulators. Experimental results of FSIM for various packet sizes, i.e., the number of test patterns simulated at a time, are also presented.

DYNAMITE: an efficient automatic test pattern generation system for path delay faults

Abstract: The authors present DYNAMITE, a versatile and efficient automatic test pattern generation system for path delay fault. Based upon a ten-valued and a three-valued logic, the deterministic test pattern generation algorithm incorporated in DYNAMITE is capable of generating both robust and nonrobust tests for path delay faults. Particular emphasis has been placed on coping with the main disadvantage of the path delay fault model. The distinct features of DYNAMITE consist of the application of a powerful implication procedure and a stepwise path sensitization procedure, which has the capability of proving large numbers of path faults as redundant by a single test generation attempt. The delay test generation process is further optimized by the use of a new path selection procedure which aims at the identification of paths, which can successfully be sensitized, and the elimination of redundant, i.e., unsensitizable, paths. >

Automating test case generation for the new generation mission software system

Abstract: The significant expansion of autonomous control and information processing capabilities in the coming generation of mission software systems results in a qualitatively larger space of behaviors that needs to be "covered" during testing, not only at the system level but also at subsystem and unit levels. A major challenge in this area is to automatically generate a relatively small set of test cases that, collectively, guarantees a selected degree of coverage of the behavior space. This paper describes an algorithm for a parametric test case generation tool that applies a combinatorial design approach to the selection of candidate test cases. Evaluation of this algorithm on test parameters from the Deep Space One mission reveals a valuable reduction in the number of test cases, when compared to an earlier home-brewed generator.