Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates

Abstract: This tutorial will give an introduction to a new defect-oriented test method called cell-aware. This new cell-aware method takes the layout of standard library cells into account when creating the cell-aware ATPG library view. The tutorial will cover the whole cell-aware library characterization flow consisting of a layout extraction step, an analog fault simulation step of all cell-internal bridges and opens and the cell-aware synthesis step to create the new cell-aware ATPG library views, which finally can be used in a normal chip design flow to generate production test patterns. These cell-aware production test patterns have a significantly higher quality than state-of-the-art patterns. Finally, production test results from several hundred thousand tested IC's are presented showing significant reduction of DPPM rates.

Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR

Abstract: This paper presents a new and efficient strategy of pseudorandom pattern generation (PRPG) for IC testing. It uses a general programmable LFSR (P-LFSR) to offer multiple-seed and multiple-polynomial PRPG. The deterministic pattern set generated by an ATPG tool or supplied by the designers is used to guide the generation of pseudorandom patterns. A novel application of the Gauss-elimination procedure is proposed to find the seeds as well as the polynomials. With an intelligent heuristic to further utilize the essential faults, this approach becomes very efficient, even for the random pattern resistant (RPR) circuits. Experiments are conducted on the ISCAS-85 benchmarks and the full scan version of the ISCAS-89 benchmarks. For all benchmark circuits, complete fault coverage is achieved with good balance on the hardware overhead and the test lengths as compared to other schemes.

On the decline of testing efficiency as fault coverage approaches 100

Abstract: Testing is an indispensable process to weed out the defective parts coming out of the manufacturing process. Traditionally, test generation targets on a specific fault model, usually the single stuck-at fault model, to produce tests that are expected to identify defects such as unintended shorts and opens. With this approach, the test quality relies on fortuitous detection of the non-target defects. As the quality demands and circuit sizes increase, the feasibility of test generation on a single fault model becomes questionable. In the paper, we present empirical data from experiments on ISCAS benchmark circuits to demonstrate that using traditional methods the probability of detecting nontarget defects drops rapidly as the fault coverage approaches 100%. By assuming surrogates, we explain the mechanism which produces this effect and describe a new test pattern generation approach with better testing efficiency.

Design for testability and built-in self-test of mixed-signal circuits: a tutorial

Abstract: The advent of new electronic packaging technologies has fueled the drive towards rapid integration of digital and analog functions particularly in portable computing and communications applications. This integration of digital and analog circuits into closely coupled mixed-signal circuits has brought with it, many challenges in the design and test areas. The problem in testing mixed-signal circuits arises from the simple fact that digital and analog fault models are inherently different. Moreover, while digital fault models are well understood (i.e. stuck-at faults), analog fault models are not quite as well-defined and mature. Another key problem stems from the fact that analog signals are inherently imprecise. Hence, with any analog measurement one must associate an accuracy of measurement. For large systems, it therefore becomes necessary to incorporate design for testability and built-in self-test (BIST) features in order to achieve high coverage of digital and analog faults. Also, with use of these features, fault simulation and test generation becomes easier. In the following paper, the authors discuss recent work in the area of design for testability and BIST.

Multi-phase test point insertion for built-in self test of integrated circuits

Abstract: Method and apparatus for providing high quality Built-In-Self-Test (BIST) of integrated circuits, while guaranteeing convergence and reducing area-overhead and power dissipation during test mode. A divide and conquer approach is used to partition the test into multiple phases during which a number of test patterns are applied to a circuit under test (CUT). The design of each phase (the selection of control and observation points) is guided by a progressively reduced list of undetected faults. Within a phase, a set of control points maximally contributing to the fault coverage achieved so far is identified using a unique probabilistic fault simulation (PFS) technique. The PFS technique accurately computes a propagation profile of the circuit and uses it to determine the impact of a new control point in the presence of control points selected so far. In this manner, in each new phase a group of control points, driven by fixed values and operating synergistically, is enabled. Observation points are selected in a similar fashion to further enhance the fault coverage. The sets of control and observation points are then inserted into the circuit under test and a new, reduced list of undetected faults is determined through exact fault simulation. This process is iterative and continues until the number of undetected faults is less than or equal to an acceptable threshold, a pre-specified number of control and observation points have been inserted, or the maximum number of specified test phases has been reached.