Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Structural Fault Testing of Embedded Cores Using Pipelining

Abstract: The purpose of this paper is to develop a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a “bypass” mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested because they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the accessibility (of the core input and output ports) is solved as a shortest path problem. Finally, a pipelined test schedule is made to overlap accessing input ports (to send test patterns) and output ports (to observe the signatures). The experimental results show higher fault coverage and shorter test time.

High defect coverage with low-power test sequences in a BIST environment

Abstract: A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digital circuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.

At-speed testing of delay faults for Motorola's MPC7400, a PowerPC/sup TM/ microprocessor

Abstract: In this paper we present the novel built-in delay fault test concepts incorporated into Motorola's MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing. A novel feature of the design is the programmable clock control circuit for issuing a given number of at-speed clocks for the delay test, once the test is initiated. Using transition and path delay fault test patterns, we have tested several MPC7400 chips at speed exceeding 540 MHz using tester speed of 63 MHz or lower.

Test time reduction in scan designed circuits

Abstract: The reduction of test application time for the general scan designed circuits has been studied. The reduction problem is investigated from three aspects: the test generation, selective scans, and rearrangement of scan path. The two phase testing strategy has been proposed to employ scan only for the hard-to-detect faults. Four cases of selective scan have also been identified. Furthermore, an ordering heuristic without layout constraint has been proposed to maximize the reduction of unnecessary scans and hence the test application time. Applying these reduction methods, the total test clock-cycles can be reduced to only 20% on average for ISCAS sequential benchmark circuits with partial scan. >

Integrating a Boolean satisfiability checker and BDDs for combinational equivalence checking

Abstract: There has been much interest in techniques which combine the advantages of function-based methods, such as BDDs, with structure-based methods, such as ATPG, for verifying the equivalence of combinational circuits. However, most existing efforts have focused on exploiting circuit similarity through use of learning and/or ATPG-based methods rather than on making the integration between BDDs and ATPG techniques efficient. This paper presents a new technique, where the focus is on improving the equivalence check itself, thereby making it more robust in the absence of circuit similarity. It is based on tight integration of a Boolean Satisfiability Checker with BDDs, whereby BDDs are effectively used to reduce both the problem size and the number of backtracks for the satisfiability problem. This methodology does not preclude exploitation of circuit similarity, when it exists, since the improved check can be easily incorporated as the inner loop of the well-known iterative framework involving search and replacement of internally equivalent nodes. We demonstrate the significance of our contributions with practical results on the ISCAS benchmark circuits.