Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Automatic configuration generation for FPGA interconnect testing

Abstract: We present a new automatic test configuration generation technique for manufacturing testing of interconnect network of SRAM-based FPGA architectures. The technique guarantees detection of open and bridging faults in all wiring channels and programmable switches in the interconnects. Only 8 test configurations are required to achieve 100% coverage of stuck-open, stuck-closed, open and bridging faults in the interconnects of Xilinx Virtex FPGAs.

Error correction code circuit that performs built-in self test

Abstract: An integrated circuit includes an ECC encoder having a normal mode of operation and a test mode of operation. During the test mode, the encoder is operated as a test pattern generator for computing a test pattern that exhaustively stimulates data paths, memory structures and other logic functions on the integrated circuit. A signature of responses to the test pattern can then be computed and compared to a known "correct" signature to determine whether timing faults and other types of faults exist in the integrated circuit. A disk controller chip based on such an integrated circuit can, in addition to testing its own on-chip data paths, memory structures and other logic functions, supply a test pattern to a read/write channel chip and other components on a printed circuit board assembly of a disk drive.

A universal test and maintenance controller for modules and boards

Abstract: The design of a versatile module test and maintenance controller (MMC) is presented. Driven by structures test programs, an MMC is able to test every chip in a module or PCB via a test bus. More than one test bus can be controlled by an MMC, and can support several bus architectures and many modes of testing. The differences between MMCs on different modules are the test programs that they execute, the number of test buses they control, and the expansion units they use. A simple yet novel circuit, called a test channel, is used in an MMC. The MMC processor can control a test channel by reading/writing its internal registers. Once initialized by the MMC processor, a test channel can carry out most of the testing of a chip. Thus the processor need not deal with detailed test-bus control sequences since they are generated by the test channel. This strategy greatly simplifies the development of test programs. The proposed MMC can be implemented as a single-chip ASIC (application-specific integrated circuit) or by off-the-shelf components. Some of its self-test features are presented. >

A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis

Abstract: Hardware Trojan Horses have emerged as great threats to modern electronic design and manufacturing practices. Because of their inherent surreptitious nature, test vector generation to detect hardware Trojan horses is a difficult problem. Efficient online detection techniques can be more effective in detection of hardware Trojan horses. In this paper, we propose a low-overhead detection technique which inserts malicious logic detection circuitry at netlist sites chosen by an algorithm that employs an intelligent and accurate analysis of fault propagation through logic gates. Proactive system-level countermeasures can be activated on detection of malicious logic, thereby avoiding disastrous system failure. Experimental results on benchmark circuits show close to 100 percent HTH detection coverage when our proposed technique is employed, as well as acceptable overheads.

Using model checking to generate fault detecting tests

Abstract: We present a technique which generates from Abstract State Machines specifications a set of test sequences capable to uncover specific fault classes. The notion of test goal is introduced as a state predicate denoting the detection condition for a particular fault. Tests are generated by forcing a model checker to produce counter examples which cover the test goals. We introduce a technique for the evaluation of the fault detection capability of a test set. We report some experimental results which validate the method, compare the fault adequacy criteria with some classical structural coverage criteria and show an empirical cross coverage among faults.