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Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.


Papers
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Proceedings ArticleDOI
20 Apr 2009
TL;DR: A test access mechanism for Adaptive Scan that addresses the problem of reducing test data and test application time in a hierarchical and low pin count environment is discussed.
Abstract: Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarchical implementations need test access mechanisms that keep the isolation between the different tests applied through the different compressors and decompressors. In this paper we discuss a test access mechanism for Adaptive Scan that addresses the problem of reducing test data and test application time in a hierarchical and low pin count environment. An active test access mechanism is used that becomes part of the compression schemes and unifies the test data for multiple CODEC implementations. Thus, allowing for hierarchical DFT implementations with flat ATPG.

39 citations

Patent
Peter Wohl1, D. F. Anastasakis1
22 Mar 2000
TL;DR: In this paper, a system and method for generating gate level descriptions tables from simulation for formal verification is presented, which can be used for both test generation and formal verification of FV models.
Abstract: A system and method for generating gate level descriptions tables from simulation for formal verification. Implementation libraries contain table-based descriptions of user defined primitives (UDPs), various-strength primitives, hierarchical structural cells and non-functional constructs, such as timing and simulation assertion checks. In order to use the library cells for use by test-generation (ATPG) and formal verification (FV), the present invention provides a library reader and a model builder that read in the library cells and construct gate-level models usable by ATPG processes. The present invention also provides a translator that accesses the ATPG models through an API (Application Programming Interface) interface and produces FV models that are usable by FV processes. Significantly, according to the present invention, the FV models are generated based on the ATPG models. Library cell complexities that would require different ATPG and FV models are automatically detected. Consequently, the single, common model is augmented with a few bits of extra information, or, in some cases, changed in a plurality of ways to accommodate different requirements of ATPG and FV.

39 citations

Journal ArticleDOI
TL;DR: A new fault modeling technique aimed at efficient simulation and test generation for complex digital MOS IC's is described and a generalized single stuck-line (GSSL) fault model is suggested as a uniform and practical method for fault representation.
Abstract: A new fault modeling technique aimed at efficient simulation and test generation for complex digital MOS IC's is described. It is based on connector-switch-attenuator (CSA) analysis, which employs purely digital models of switching transistors, resistive/capacitive elements, and their associated signals. The use of CSA networks to model the digital behavior, both static and dynamic, of MOS circuits is reviewed. It is shown that most physical failure modes in such circuits, including short-circuit, open-circuit, and delay faults, can be modeled more efficiently by CSA models than by conventional approaches. A generalized single stuck-line (GSSL) fault model is suggested as a uniform and practical method for fault representation.

39 citations

Journal ArticleDOI
H. Cox1, Janusz Rajski1
TL;DR: Algorithms based on the mathematical properties of images and inverse images of set functions to define reduction and tendency lists in combinational logic circuits, used to identify necessary and nonconflicting assignments, respectively are presented.
Abstract: Necessary, nonconflicting, and arbitrary assignments can be distinguished during algorithmic test pattern generation. The identification of necessary and nonconflicting assignments is algorithmic in the sense that there is no element of choice or luck in the computation, no reliance on heuristics, and no possibility of these assignments causing a backtrack if the fault is testable. This paper presents algorithms based on the mathematical properties of images and inverse images of set functions to define reduction and tendency lists in combinational logic circuits, used to identify necessary and nonconflicting assignments, respectively. Issues relating to the efficient implementation of these algorithms are addressed from both a theoretical and practical perspective. Experimental results obtained on a variety of benchmark circuits show that algorithmic assignment identification can be used to reduce or eliminate backtracking in automatic test pattern generation. >

39 citations

Proceedings ArticleDOI
18 Mar 2002
TL;DR: This paper presents a hybrid BIST architecture and methods for optimizing it to test system-on-chip in a cost effective way and demonstrates the feasibility and efficiency of the approach, and significant decreases in overall test cost.
Abstract: This paper presents a hybrid BIST architecture and methods for optimizing it to test system-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns with stored deterministic test patterns to perform core test with minimum time and memory, without losing test quality. We propose two algorithms to calculate the cost of the rest process. To speed up the optimization procedure, a Tabu search based method is employed for finding the global cost minimum. Experimental results have demonstrated the feasibility and efficiency of the approach and the significant decreases in overall test cost.

39 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202338
202278
202125
202048
201980
201869