Topic
Automatic test pattern generation
About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.
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TL;DR: Current ATPG techniques and efforts to adapt ATPG technology to handle deep-submicron faults and to identify design errors and timing problems during design verification are described.
Abstract: Test development automation tools, which automate dozens of tasks essential for developing adequate tests, generally fall into four categories: design for testability (DFT), test pattern generation, pattern-grading, and test program development and debugging. The focus in the article is on automatic test-pattern-generation tools. Researchers have looked primarily at issues such as scalability, ability to handle various fault models, and how to extend the algorithms beyond Boolean domains to handle different abstraction levels. Their aims were to speed up test generation, reduce test sequence length, and minimize power consumption. As design trends move toward nanometer technology however, new ATPG problems are emerging. Current modeling and vector generation techniques must give way to new techniques that consider timing information during test generation, scale to larger designs, and can capture extreme design conditions. The authors describe current ATPG techniques and efforts to adapt ATPG technology to handle deep-submicron faults and to identify design errors and timing problems during design verification.
37 citations
TL;DR: This paper proposes a new approach to reduce test data volume and test cycle count in scan-based testing by assuming a 1-to-1 scan configuration, in which the number of internal scan chains equals thenumber of external scan I/O ports or test channels from ATE.
Abstract: IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.
37 citations
TL;DR: A logic system specifically designed for fault test generation that allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration.
Abstract: This paper describes a logic system specifically designed for fault test generation. The system allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration. He can be as vague or as specific as he wants in imposing these constraints. A set of logic tables is then used to automatically propagate the effects of these constraints throughout the network. As a result of this logic propagtion, the necessary values of the elements in the network become much more precisely (if not completely) defined. The tables also indicate whether or not the generated test (which may include a number of unspecified values) is sufficient to detect the given fault. If several different tests will suffice, the choices remaining are clearly indicated. In the case of a redundant lead (untestable fault), propagation through the tables automatically results in a logical inconsistency.
37 citations
18 Oct 1998
TL;DR: An automatic tool called GateMaker is described, that has been developed to extract a gate level schematic model from a transistorlevel schematic model for the purposes of logic simulation, fault simulation and automatic test pattern generation.
Abstract: Hierarchy is key to managing design complexity. A hierarchical design system needs to maintain many views of the same design entity. Some of the examples might be physical view for placement routing and extraction; transistor schematic view for circuit simulation, timing characterization and noise analysis; a gate level schematic view for timing, verification, logic simulation, fault simulation and automatic lest pattern generation (ATPG); a register transfer level (RTL) view for specification and high level simulation etc. In order to achieve highest system performance, multiple design iterations are necessary, each iteration involving both forward and backward pass through hierarchy, with manual changes at any level of the hierarchy. This poses an essential challenge of keeping all views of same design entity in sync. In this paper we describe an automatic tool called GateMaker, that has been developed to extract a gate level schematic model from a transistor level schematic model for the purposes of logic simulation, fault simulation and automatic test pattern generation. This eliminates a manual process and offers manifold advantages that will be discussed in this paper.
37 citations
06 May 2007
TL;DR: A novel low power test scheme integrated with the embedded deterministic test environment reduces switching rates in scan chains with no hardware modification and results obtained indicate that switching activity can be reduced up to 23 times.
Abstract: This paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces switching rates in scan chains with no hardware modification. Experimental results obtained for industrial circuits indicate that switching activity can be reduced up to 23 times.
37 citations