Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

A unified framework for design validation and manufacturing test

Abstract: New approaches to address the difficult problems in test are necessary if its current status as a major bottleneck in the production of quality integrated circuits is to be changed. The authors propose a new direction for solving the test problem using powerful methods already employed for the formal verification of large circuits. More specifically, they discuss how abstraction techniques can assist conventional ATPG tools when attacking hard to detect faults. The same abstractions can also be used in design verification to increase the level of confidence in a design following simulation, by providing a meaningful measure of the coverage achieved by the verification vectors. In this sense, the authors' approach is geared toward providing a unified fled framework for design validation and manufacturing test.

Processor-programmable memory BIST for bus-connected embedded memories

Abstract: We present a processor-programmable built-in self-test (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced.

Control-aware test architecture design for modular SOC testing

Abstract: This paper deals with control-aware test architecture design for SOCs. The term test control refers to the control of mode of operation of all modules connected in different TAMs and the execution of the modules tests. We classify test control into two categories: (1) pseudo-static test control and (2) dynamic test control. Pseudo-static test control can be provided by means of a shift-register, where dynamic test control requires dedicated test pins. As the total number of chip pins available for test is limited, a large number of test control pins results in less TAM bandwidth available for test data. Therefore test architecture design should take the test control into account. To deal with pseudo-static test control for a given test architecture, we present two test strategies and discuss their impact on the corresponding test schedule. For dynamic test control, we present pin-constrained design of test architectures. Experimental results for the ITC'02 SOC test benchmarks show that the new pin-constrained design algorithm can save tip to 42 % in test time compared to the test times obtained from a conventional architecture design procedure.

I/sub DDQ/ test and diagnosis of CMOS circuits

Abstract: Designers must target realistic faults if they desire high-quality test and diagnosis of CMOS circuits. The authors propose a strategy for generating high-quality I/sub DDQ/ test patterns for bridging faults. They use a standard ATPG tool for stuck-at faults that adapts to target bridging faults via I/sub DDQ/ testing. The authors discuss I/sub DDQ/ test set diagnosis capability and specifically generated vectors that can improve diagnosability, and provide test and diagnosis results for benchmark circuits.

False coupling interactions in static timing analysis

Abstract: Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. In order to avoid excessive conservatism in static timing analysis, it is important to determine if aggressor lines can potentially switch simultaneously with the victim. In this paper, we present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. We present results on several benchmark circuits that show the value of considering functional information to reduce the conservatism associated with worst-case coupled line switching assumptions during static timing analysis.