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Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.


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Patent
05 Oct 2007
TL;DR: In this article, a built-in self-test (BIST) circuit is presented that allows high fault coverage and a method is disclosed for implementing the BIST circuit. But the method is limited to the use of a single scan chain.
Abstract: A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains.

37 citations

Proceedings ArticleDOI
30 Apr 1995
TL;DR: The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor and a method to design and testmicropipelines is presented.
Abstract: The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques.

37 citations

Patent
22 Jun 2000
TL;DR: In this paper, a test system for structurally testing an integrated circuit device includes a pattern generator for generating successive random data patterns (scan chain), and a constraint checker and corrector module, coupled to the pattern generator, to replace undesirable bit sequences with desirable bit sequences to eliminate bus contention problems in the generated random data pattern.
Abstract: A test system for structurally testing an integrated circuit device includes a pattern generator for generating successive random data patterns (scan chain). The test system further includes a constraint checker and corrector module, coupled to the pattern generator, to replace undesirable random data patterns (state elements joined together in the scan chain such that one state element is connected to a ground and the other state element is connected to a power supply) with desirable bit sequences to eliminate bus contention problems in the generated random data patterns. The test system further includes the integrated circuit device to be tested. The integrated circuit device receives the constrained random data patterns from the constraint checker and corrector module and outputs a test result. The test system further includes an X-masking module coupled to the integrated circuit device. The X-masking module receives the test result from the integrated circuit device, and it masks the test result by replacing unpredictable bit values (these are bit values generated due to not scanning some state elements in the scan chain) in the test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compress the test result into a signature. Then a comparator coupled to the signature analyzer compares the signature with a predetermined test result to determine the functionality of the integrated circuit device.

37 citations

Proceedings ArticleDOI
06 Mar 1995
TL;DR: A defect-oriented test methodology for mixed analog-digital circuits is proposed, shown that with simple tests 93% of the defects in this circuit can be detected and application of DfT guidelines derived from this test methodology may improve the defect coverage to 99%.
Abstract: Testing of analog blocks in digital circuits is emerging as a critical factor in the success of mixed-signal ICs. The present specification-oriented testing of these blocks results in high test costs and doesn't ensure detection of all defects, causing potential reliability problems. To solve these problems, in this paper a defect-oriented test methodology for mixed analog-digital circuits is proposed. The strength of the method is demonstrated by an implementation for a complex mixed-signal circuit, a flash analog-to-digital converter. It is shown that with simple tests 93% of the defects in this circuit can be detected. Moreover application of DfT guidelines derived from this test methodology may improve the defect coverage to 99%. First impressions lead to the conclusion that the analyzed test obtains a higher defect coverage with lower test costs than functional tests. >

37 citations

Proceedings ArticleDOI
28 Apr 1995
TL;DR: This paper analyzes the pattern sequences produced by different types of accumulators and shows that they can achieve similar fault coverage as pseudo-random patterns.
Abstract: Configurations of adders and registers, which are available in many datapaths, can be utilized to generate patterns and to compact test responses. This paper analyzes the pattern sequences produced by different types of accumulators and shows that they can achieve similar fault coverage as pseudo-random patterns. Compared to the well-known self-test methods that insert test registers, the approach using accumulators saves the additional gates that are needed to implement test registers, and it avoids performance degradation due to additional delays.

37 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202338
202278
202125
202048
201980
201869