Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Economic effects in design and test

Abstract: The authors argue that because of misconceptions and myths about the cost of test, many devices and systems are inadequately tested. Focusing on application-specific integrated circuits (ASICs), the authors discuss the economics of test and show how economic analysis leads to test that pays back. The EVEREST test strategy planner, a design tool that aids in the selection of design-for-testability structures during ASIC design and uses cost as a primary selection parameter, is presented. >

Test generation for crosstalk-induced faults: framework and computational results

Abstract: Due to technology scaling and increasing clock frequency, problems due to noise effects are leading to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk-induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times and gate delay. In this paper, we first discuss the general framework of the test generation algorithm followed by computational results. A comparison of our results with SPICE simulations confirms the accuracy of this approach.

AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis

Abstract: Reusing embedded resources for implementing built- in self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement cost- efficient built-in self test functions from the AES cryptoalgorithm hardware implementation in a secure system. Self-test of the proposed implementation is also presented. A statistical test suite and fault-simulation are used for evaluating the efficiency of the corresponding cryptocore as pseudo-random test pattern generator; an analytical approach demonstrates the low probability of aliasing when used for test response compaction.

Deterministic BIST architecture tolerant of uncertain scan chain outputs

Abstract: A BIST architecture that allows efficient compression and application of deterministic ATPG patterns while tolerating uncertain bits is provided. In accordance with one feature of the invention, a large number of short scan chains can be configured between a decompressor and an observe selector. The observe selector selectively presents values of specific scan chains or scan cells to an external tester, thereby significantly reducing test data and test cycles. Advantageously, the core of the tested device is not changed as would be the case in BIST architectures including MISRs. Moreover, test points or logic to block uncertain bits do not need to be inserted. Furthermore, the loaded care bits for the scan chains as well as the bits for controlling the observe selector can be deterministically controlled, thereby providing optimal testing flexibility.

On the initialization of sequential circuits

Abstract: A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented. This method is based on structural decomposition of the circuit, and can handle both logical (using X-value simulation) and functional initializabilities. Results for some benchmark circuits are also presented.