Topic
Automatic test pattern generation
About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.
Papers published on a yearly basis
Papers
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TL;DR: The power test as discussed by the authors is a combination of the extended GCD algorithm and the Fourier-Motzkin method to eliminate variables in a system of inequalities, which is the first test that can generate the information needed for some advanced transformations, and that can handle complex simultaneous loop limits.
Abstract: A data dependence decision algorithm called the power test is introduced. The power test is a combination of the extended GCD algorithm and the Fourier-Motzkin method to eliminate variables in a system of inequalities. This is the first test that can generate the information needed for some advanced transformations, and that can handle complex simultaneous loop limits. Previous work in data dependence decision algorithms is reviewed. Some examples which motivated the development of this test are examined, including those which demonstrate the additional power of the power test. Although it may be too expensive for use as a general-purpose dependence test in a compiler, the power test has proved useful in an interactive program restructuring environment. >
144 citations
IBM1
TL;DR: A new, "directed" test-generation technique, which aims to maximize the similarity between the path constraints of the generated tests and those of faulty executions, reaches this level of effectiveness with much smaller test suites, when compared to test generation based on standard concolic execution techniques.
Abstract: Fault-localization techniques that apply statistical analyses to execution data gathered from multiple tests are quite effective when a large test suite is available. However, if no test suite is available, what is the best approach to generate one? This paper investigates the fault-localization effectiveness of test suites generated according to several test-generation techniques based on combined concrete and symbolic (concolic) execution. We evaluate these techniques by applying the Ochiai fault-localization technique to generated test suites in order to localize 35 faults in four PHP Web applications. Our results show that the test-generation techniques under consideration produce test suites with similar high fault-localization effectiveness, when given a large time budget. However, a new, "directed" test-generation technique, which aims to maximize the similarity between the path constraints of the generated tests and those of faulty executions, reaches this level of effectiveness with much smaller test suites. On average, when compared to test generation based on standard concolic execution techniques that aims to maximize code coverage, the new directed technique preserves fault-localization effectiveness while reducing test-suite size by 86.1% and test-suite generation time by 88.6%.
143 citations
TL;DR: Block minimized test sets have a size/effectiveness advantage, in terms of a significant reduction in test set size and with almost the same fault detection effectiveness, over the original non-minimized test sets.
142 citations
28 Sep 1999
TL;DR: A model is presented to evaluate the effect of parasitic coupling crosstalk and conditions for the creation of the worst-case coupling and propagation of a delayed signal are presented.
Abstract: Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper shows how crosstalk coupling between lines can affect the propagation delay of signals in integrated circuits. A model is presented to evaluate the effect of parasitic coupling crosstalk. Conditions for the creation of the worst-case coupling and propagation of a delayed signal are presented. A test pattern generation algorithm utilizing the above conditions is presented and applied to several example circuits.
142 citations
TL;DR: The design for testability (DFT) of active analog filters based on oscillation-test methodology is described and the DFT techniques investigated are very suitable for automatic testable filter synthesis and can be easily integrated in the tools dedicated to automatic filter design.
Abstract: The oscillation-test strategy is a low cost and robust test method for mixed-signal integrated circuits. Being a vectorless test method, it allows one to eliminate the analog test vector generator. Furthermore, as the oscillation frequency is considered to be digital, it can be precisely analyzed using pure digital circuitry and can be easily interfaced to test techniques dedicated to the digital part of the circuit under test (CUT). This paper describes the design for testability (DFT) of active analog filters based on oscillation-test methodology. Active filters are transformed to oscillators using very simple techniques. The tolerance band of the oscillation frequency is determined by a Monte Carlo analysis taking into account the nominal tolerance of all circuit under test components. Discrete practical realizations and extensive simulations based on CMOS 1.2 /spl mu/m technology parameters affirm that the test technique presented for active analog filters ensures high fault coverage and requires a negligible area overhead. Finally, the DFT techniques investigated are very suitable for automatic testable filter synthesis and can be easily integrated in the tools dedicated to automatic filter design.
141 citations