Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis

Abstract: In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A fault situation specifies faulty as well as fault-free lines. Other applications include identifying the existence of nonstuck faults in N* and determination of faults not detected by a given test, including redundant faults. The latter application allows for the generation of tests for multiple faults without performing fault enumeration.

Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration

Abstract: Finite state machine (FSM) verification based on implicit state enumeration can be extended to test generation and redundancy identification. The extended method constructs the product machine of two FSMs to be compared, and reachability analysis is performed by traversing the product machine to find any difference in I/O behavior. When an output difference is detected, the information obtained by reachability analysis is used to generate a test sequence. This method is complete, and it generates one of the shortest possible test sequences for a given fault. However, applying this method indiscriminately for all faults may result in unnecessary waste of computer resources. An efficient method based on reachability analysis of the fault-free machine (three-phase ATPG) in addition to the powerful but more resource-demanding product machine traversal is presented. The application of these algorithms to the problems of generating test sequences, identifying redundancies, and removing redundancies is reported. >

On static compaction of test sequences for synchronous sequential circuits

Abstract: We propose three static compaction techniques for test sequences of synchronous sequential circuits. We apply the proposed techniques to test sequences generated for benchmark circuits by various test generation procedures. The results show that the test sequences generated by all the test generation procedures considered can be significantly compacted. The compacted sequences thus have shorter test application times and smaller memory requirements. As a by product, the fault coverage is sometimes increased as well. More importantly, the ability to significantly reduce the length of the test sequences indicates that it may be possible to reduce test generation time if superfluous input vectors are not generated.

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

Abstract: We propose satisfiability checking (SAT) techniques that lead to a consistent performance improvement of up to 3/spl times/ over state-of-the-art SAT solvers like Chaff on important problem domains in VLSI CAD. We observe that in circuit oriented applications like ATPG and verification, different software engineering techniques are required for the portions of the formula corresponding to learnt clauses compared to the original formula. We demonstrate that by employing the same innovations as in advanced CNF-based SAT solvers, but in a hybrid approach where these two portions of the formula are represented differently and processed separately, it is possible to obtain the consistently highest performing SAT solver for circuit oriented problem domains. We also present controlled experiments to highlight where these gains come from. Once it is established that the hybrid approach is faster, it becomes possible to apply low overhead circuit-based heuristics that would be unavailable in the CNF domain for greater speedup.

Detection of Faults in Programmable Logic Arrays

Abstract: A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required by exhaustive testing. Finally, it is shown that many interesting classes of multiple faults are also detected by the test sets.