Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

PROTEST: A Tool for Probabilistic Testability Analysis

Abstract: The CAD-tool PROTEST (Probabilistic Testability Analysis) is presented PROTEST estimates for each fault of a combinational circuit its detection probability which can be used as a testability measure Moreover it calculates the number of random test patterns which must be generated in order to achieve the required fault coverage It is also demonstrated that the fault coverage will increase and the necessary number of random patterns will drastically decrease, if each primary input is stimulated by test patterns having specific probabilities of being logical "1" PROTEST uses this fact and determines for each input the optimal signal probability for a randomly generated pattern

Reduction of SOC test data volume, scan power and testing time using alternating run-length codes

Abstract: We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time and scan power. The proposed approach is based on the use of alternating run-length codes for test data compression. Experimental results for the larger ISCAS-89 benchmarks and an IBM production circuit show that reduced test data volume, test application time and low power scan testing can indeed be achieved in all cases.

Instruction randomization self test for processor cores

Abstract: Access to embedded processor cores for application of test has greatly complicated the testability of large systems on silicon. Scan based testing methods cannot be applied to processor cores which cannot be modified to meet the design requirements for scan insertion. Instruction Randomization Self Test (IRST) achieves stuck-at-fault coverage for an embedded processor core without the need for scan insertion or mux isolation for application of test patterns. This is a new built-in self test method which combines the execution of microprocessor instructions with a small amount of on-chip test hardware which is used to randomize those instructions. IRST is well suited for meeting the challenges of testing ASIC systems which contain embedded processor cores.

ITC'99 Benchmark Circuits - Preliminary Results

Abstract: The goal of this benchmarking effort is to test new DFT techniques on these real designs. Six panelists will present their preliminary results. Mario Konijnenburg of Philips will present full scan test generation results as a baseline, using the DAT test generation system. Raghuram Tupuri will present results from a hierarchical test generator, creating at-speed tests using functional knowledge without the need for scan. Professor J-E Santucci will describe a test generator for design verification tests, using techniques derived from software testing. Professor S . M. Reddy will describe results from two sequential test generators developed at the University of Iowa. Dr. Chouki Aktouf will describe techniques for the insertion of scan at the functional level. Professor Sujit Dey will describe the testabiiity of one of the benchmarks, and some functional BIST approaches.

Abstraction techniques for validation coverage analysis and test generation

Abstract: The enormous state spaces which must be searched when verifying the correctness of, or generating tests for, complex circuits precludes the use of traditional approaches. Hard-to-find abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. This control flow, capturing the essential "behavior" of the circuit, is represented as a finite state machine called the ECFM (Extracted Control Flow Machine). Simulation is currently the primary means of verifying large circuits, but the definition of a coverage measure for simulation vectors is an open problem. We define functional coverage as the amount of control behavior covered by the test suite. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph. We also demonstrate how the same abstraction techniques can complement ATPG techniques when attacking hard-to-detect faults in the control part of the design for which conventional ATPG alone proves to be inadequate or inefficient at best. Results on large designs show significant improvement over conventional algorithms.