Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Timing analysis and delay-fault test generation using path-recursive functions

Abstract: The authors introduce an efficient method for generating the functional forms of path analysis problems. They demonstrate that the resulting function is linear in the size of the circuit. The functions are then tested for satisfiability either using a Boolean network satisfiability algorithm suggested by T. Larrabee (1989) or through the construction of BDDs. The effectiveness of the proposed approach is shown for timing analysis and robust path delay-fault test generation. This method also holds promise for both static and dynamic hazard analysis, and for test generation using all other delay-fault models, tau -irredundant fault models, and stuck-open fault models. >

Transition fault testing for sequential circuits

Abstract: Addresses the problem of simulating and generating tests for transition faults in nonscan and partial scan synchronous sequential circuits. A transition fault model for sequential circuits is first proposed. In this fault model, a transition fault is characterized by the fault site, the fault type, and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. Fault simulation and test generation algorithms for this fault model are presented. The fault simulation algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. Experimental results show that neither a comprehensive functional verification sequence nor a test sequence generated by a sequential circuit test generator for stuck faults produces a high fault coverage for transition faults. Deterministic test generation for transition faults is required to raise the coverage to a reasonable level. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck fault test generation algorithm with some modifications. Experimental results for ISCAS-89 benchmark circuits and some AT&T designs are presented. Modifications to test generation and fault simulation algorithms required for partial scan circuits are presented. Experimental results on large benchmark circuits show that a high transition fault coverage can be achieved for the partial scan circuits designed using the cycle breaking technique. >

Robust search algorithms for test pattern generation

Abstract: In recent years several highly effective algorithms have been proposed for Automatic Test Pattern Generation (ATPG). Nevertheless, most of these algorithms too often rely on different types of heuristics to achieve good empirical performance. Moreover there has not been significant research work on developing algorithms that are robust, in the sense that they can handle most faults with little heuristic guidance. In this paper we describe an algorithm for ATPG that is robust and still very efficient. In contrast with existing algorithms for ATPG, the proposed algorithm reduces heuristic knowledge to a minimum and relies on an optimized search algorithm for effectively pruning the search space. Even though the experimental results are obtained using an ATPG tool built on top of a Propositional Satisfiability (SAT) algorithm, the same concepts can be integrated on application-specific algorithms.

3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits

Abstract: A method for weighted pseudorandom test generation based on a deterministic test set is described. The main advantages of the method described over existing methods are: (1) only three easily generated weights (0, 0.5 and 1) are used, (2) a minimum number of shift register cells is used, thus leading to minimal hardware for built-in-test applications, and (3) the weights are selected to allow the same coverage of target faults attained by the deterministic test set to be attained by weighted random patterns. The weights are computed by walking through the range of test generation approaches from pure random at one extreme to deterministic at the other extreme, dynamically selecting the weight assignments to correspond to the remaining faults at every stage. Hardware suitable for the generation of random patterns under the proposed method is described. The method is suitable for both combinational and sequential circuits. Experimental results are provided for ISCAS-85 and MCNC benchmark circuits. >

SMART And FAST: Test Generation for VLSI Scan-Design Circuits

Abstract: This article describes new concepts and algorithms used to generate tests for VLSI scan-design circuits. The new algorithms include: 1. a low-cost fault-independent algorithm (SMART), 2. a fault-oriented algorithm (FAST), and 3. an algorithm for dynamic test set compaction. The fault-oriented algorithm is guided by new controllability/observability cost functions whose objective is to minimize the amount of search done in test generation.