Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

An automatic test pattern generator for large sequential circuits based on Genetic Algorithms

Abstract: This paper is concerned with the question of automated test pattern generation for large synchronous sequential circuits and describes an approach based on Genetic Algorithms suitable for even the largest benchmark circuits, together with a prototype system named GATTO. Its effectiveness (in terms of result quality and CPU time requirements) for circuits previously unmanageable is illustrated. The flexibility of the new approach enables users to easily trade off fault coverage and CPU time to suit their needs.

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Abstract: Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.

Implicit test generation for behavioral VHDL models

Abstract: This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage, in particular when considering circuits with hard to detect faults.

Design of compactors for signature-analyzers in built-in self-test

Abstract: Originally developed decades ago, logic built-in self-test (BIST) evolved and is now increasingly being adopted to cope with rapid growth in design size and complexity. Compared to deterministic pattern test, logic BIST requires many more test patterns, and therefore, increased test time unless many more internal scan chains can be shifted in parallel. To match this large number of scan chains, the width of the signature analyzer would have to be enlarged, which would result in large area overhead and signature storage space. Instead, a combinational space-compactor is inserted between the scan chain outputs and the signature analyzer inputs. However, the compactor may deteriorate the ability to test and diagnose the design. This paper analyzes how compactors affect test and diagnosis and shows that compactors can be designed to actually improve the testability of certain faults, while providing full diagnosis capability. Algorithms that allow automated design of optimal compactors are presented and results are discussed.