Topic
Automatic test pattern generation
About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.
Papers published on a yearly basis
Papers
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01 Nov 1997TL;DR: The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties.
Abstract: This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient.
72 citations
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01 Nov 1997
TL;DR: The key idea of the proposed method is to perform the Burrows-Wheeler transformation on the sequence of test patterns, and then to apply run-length coding, and the experimental results show that the compression method performs better than six other methods for compressing test data.
Abstract: The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. A compression algorithm for test data should meet two requirements: lossless and simple decompression. In this paper we propose a new test data compression method that aims to fully utilize the unique characteristics of test data compression. The key idea of the proposed method is to perform the Burrows-Wheeler transformation on the sequence of test patterns, and then to apply run-length coding. The experimental results show that our compression method performs better than six other methods for compressing test data. The average compression ratio of the proposed method performed on five test data sets is 315, while that for the next best one, the LZW method, is 21.
72 citations
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TL;DR: This paper addresses the fault diagnosis issue based on a simulation before test philosophy in analog electronic circuits by proposing a novel method for constructing the fault dictionary under the single faulty component/unit hypothesis.
Abstract: This paper addresses the fault diagnosis issue based on a simulation before test philosophy in analog electronic circuits. Diagnosis, obtained by comparing signatures measured at the test nodes with those contained in a fault dictionary, allows for sub-systems testing and fault isolation within the circuit. A novel method for constructing the fault dictionary under the single faulty component/unit hypothesis is proposed. The method, based on a harmonic analysis, allows for selecting the most suitable test input stimuli and nodes by means of a global sensitivity approach efficiently carried out by randomized algorithms. Applicability of the method to a wide class of circuits and its integration in diagnosis tools are granted since randomized algorithms assure that the selection problem can be effectively carried out with a poly-time algorithm independently from the fault space, structure, and complexity of the circuit.
72 citations
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18 Oct 1998TL;DR: The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators in a time-efficient manner.
Abstract: The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators. The algorithms presented in the paper synthesize in a time-efficient manner very large and fast phase shifters for built in self-test environment, with guaranteed minimal phase shifts between scan chains, and very low delay and area of virtually one 2-way XOR gate per channel.
71 citations
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01 Jun 1991TL;DR: An algorithm that uses dynamic programming to order IC tests so that faulty circuits are detected early in the test sequence and the average test time is minimized is described.
Abstract: This paper describes an algorithm that uses dynamic programming to order IC tests so that faulty circuits are detected early in the test sequence and the average test time is minimized. An accurate estimate of the probabilities of individual tests failing, and the joint probabilities of several tests failing is required. These probabilities can be estimated using statistical simulation techniques or from actual circuits. The ordering algorithm is O(mn2") where n is the number of tests to be ordered, and m is the number of data points.
71 citations