Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

Integration of non-classical faults in standard March tests

Abstract: New fault models like the unrestored write and the false write through faults and suitable test algorithms have recently been developed by several authors. These tests are applied in addition to March tests. Since a March test algorithm can be implemented in many different ways and still be effective in detecting its target faults, we have what we call degrees of freedom in the test space. In this paper it is shown, that for commonly used memory organizations tests for the unrestored write and false write through faults can be integrated in March test sequences. It is shown how to design address sequence generators and address dependent data for March tests, that generate all the patterns required for the detection of those faults. The detection properties of the original March tests are retained. The additional overhead in terms of silicon area and timing for an on-chip realization of a built-in March self-test with the added fault detection features is negligible and the test application time remains unchanged.

Method of and system for dynamic automated test case generation and execution

Abstract: An automated system that randomly generates test cases for use in hardware or software quality assurance testing, wherein a given test case comprises a sequence (or “chain”) of discrete, atomic steps (or “building blocks”). A particular test case (i.e., a given sequence) has a variable number of building blocks. The system takes a set of test actions (or even test cases) and links them together in a relevant and useful manner to create a much larger library of test cases or “chains.” The chains comprise a large number of random sequence tests that facilitate “chaos-like” or exploratory testing of the overall system under test. Upon execution in the system under test, the test case is considered successful (i.e., a pass) if each building block in the chain executes successfully; if any building block fails, the test case, in its entirety, is considered a failure. The system adapts and dynamically generates new test cases as underlying data changes (e.g., a building block is added, deleted, modified) or new test cases themselves are generated. The system also is tunable to generate test sequences that have a given (e.g., higher) likelihood of finding bugs or generating errors from which the testing entity can then assess the system operation. Generated chains can be replayed easily to provide test reproducibility.

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity

Abstract: Low-power design looks for low-energy BIST. This paper considers the problem of minimizing the energy required to test a BISTed combinational circuit without modifying the stuck-at fault coverage and with no extra area or delay overhead over the classical LFSR architectures. The objective of this paper is twofold. First, is to analyze the impact of the polynomial and seed selection of the LFSR used as TPG on the energy consumed by the circuit. It is shown that appropriately selecting the seed of the LFSR can lead to an important energy reduction. Second, is to propose a method to significantly decrease the energy consumption of BIST sessions. For this purpose, a heuristic method based on a simulated annealing algorithm is briefly described in this paper. Experimental results using the ISCAS benchmark circuits are reported, showing variations of the weighted switching activity ranging from 147% to 889% according to the seed selected for the LFSR. Note that these results are always obtained with no loss of stuck-at fault coverage.

Application of simple genetic algorithms to sequential circuit test generation

Abstract: In this work we investigate the effectiveness of genetic algorithms (GAs) in the test generation process. We use simple GAs to generate populations of candidate test vectors and to select the best vector to apply in each time frame. A sequential circuit fault simulator is used to evaluate the fitness of each candidate vector, allowing the test generator to be used for both combinational and sequential circuits. We experimented with various GA parameters, namely population size, number of generations, mutation rate, and selection and crossover schemes. For the ISCAS85 combinational benchmark circuits, 100% of testable faults were detected in six of the ten circuits used, and very compact test sets were generated. Good results were obtained for many of the ISCAS89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases. >

PACOGEN: Automatic Generation of Pairwise Test Configurations from Feature Models

Abstract: Feature models are commonly used to specify variability in software product lines. Several tools support feature models for variability management at different steps in the development process. However, tool support for test configuration generation is currently limited. This test generation task consists in systematically selecting a set of configurations that represent a relevant sample of the variability space and that can be used to test the product line. In this paper we propose \pw tool to analyze feature models and automatically generate a set of configurations that cover all pair wise interactions between features. \pw tool relies on constraint programming to generate configurations that satisfy all constraints imposed by the feature model and to minimize the set of the tests configurations. This work also proposes an extensive experiment, based on the state-of-the art SPLOT feature models repository, showing that \pw tool scales over variability spaces with millions of configurations and covers pair wise with less configurations than other available tools.