Automatic test pattern generation

About: Automatic test pattern generation is a research topic. Over the lifetime, 8214 publications have been published within this topic receiving 140773 citations. The topic is also known as: ATPG.

LSI logic testing — An overview

Abstract: The development of large scale integration (LSI) testing is reviewed. The paper concentrates on the testing of logic components and presents in-depth discussions of the methods of fault modeling, test pattern generation, fault simulation, and design for testability. It is shown how these methods are used in the design of components and how they can be used in support of design automation. Finally, a brief account of test equipment and test data preparation is given.

Built-in self-testing of random-access memories

Abstract: Built-in self-test (BIST) methods are examined, including the fault models and the test algorithms on which the BIST implementations are based. The notion of generic test architectures suitable for implementing a wide variety of test algorithms is introduced. A taxonomy for test architectures is provided and used to categorize BIST implementations, and important implementations are surveyed. It is demonstrated that BIST is a viable solution to the problem of testing large memories and that approaches based on test architectures rather than on test algorithms are more versatile and will likely predominate in the future. >

Test point insertion that facilitates ATPG in reducing test time and data volume

Abstract: Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means of test point insertion (TPI). The state-of-the-art TPI methods only focus on solving one or two possible testability problems, and sometimes even fail to result in test set size reduction because they focus on the wrong testability problem. In this paper, we propose two TPI pre-process methods that analyze the circuit and select the TPI method that will focus on the testability problems that really exist. Experimental results indicate that with these pre-processes, better test set size reductions can be achieved. Gate-delay fault ATPG test sets tend to be even larger than stuck-at fault ATPG test sets. In this paper we have evaluated the impact of TPI on gate-delay fault test sets. Experimental results indicate that TPI also results in a significant test set size reduction for gate-delay fault ATPG.

An improved method for RTL synthesis with testability tradeoffs

Abstract: A method for high level synthesis with testability is presented with the objective to generate self-testable RTL datapath structures. We base our approach on a new improved testability model that generates various testable design styles while reducing the circuit sequential depth from controllable to observable registers. We follow the allocation method with an automatic test point selection algorithm and with an interactive tradeoff scheme which trades design area and delay with test quality. The method has been implemented and design comparisons are reported.

Finding defects with fault models

Abstract: A process is presented to validate fault models used in fault diagnosis. Known defects are inserted, using a focused ion beam (FIB), into production ICs and their behavior is compared to that predicted in fault simulation. The fault model is refined until it matches the observed defect behavior. The process is then repeated with known defects in unknown ("blind") locations, and necessary modifications to the model are again made. Finally, the model is used to diagnose chips with unknown defects. Experimental results on several chips demonstrate the value of the approach, which can be extended to test pattern generation and test quality estimation as well as fault diagnosis.