Back-side bus

About: Back-side bus is a research topic. Over the lifetime, 3808 publications have been published within this topic receiving 65305 citations.

Integrated circuit I/O using a high performance bus interface

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

System and method for performing secure device communications in a peer-to-peer bus architecture

Abstract: A system and method for performing secure peer-to-peer device communications on an I/O bus, such as a PCI bus, a Fiber Channel bus, an IEEE, 1394 bus or a Universal Serial Bus. The system includes a plurality of intelligent I/O devices, such as intelligent storage devices and/or controllers, communications devices, video devices and audio devices. The I/O devices perform peer-to-peer message and data transfers, thereby bypassing the operating system running on the computer's CPU. The intelligent I/O devices encrypt messages and data before transmitting them on the I/O bus and conversely decrypt the messages and data upon reception. The encryption provides secrecy and/or authentication of the sender. The devices use keys or passwords to encrypt/decrypt the data. The keys are stored in non-volatile memory in the devices and are distributed to the devices by the system BIOS at initialization time. The devices perform access authorization validation using rule sets also distributed by the BIOS at initialization time. The rule sets specify which I/O operations are valid for a peer I/O device to request of a respective I/O device based, preferably, upon the device class/subclasses of the requesting device. In another embodiment, one of the intelligent I/O devices may be a communications device which serves as a firewall for the I/O bus. In this embodiment, the rule set further includes identification information of the remote machines/devices.

Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width

Abstract: An integrated circuit (2210) provides on a single chip for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor-related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third terminals for memory-related signals (of 2258), and a DRAM memory controller (2250) connected to the third terminals. Further on chip is provided an arbiter circuit (2230), a bus bridge circuit (2236) coupled to the DRAM memory controller and to the second terminals, the bus bridge (2236) also coupled to the arbiter (2230), a second processor (2224) having a second data width (16-bit), and a bus interface circuit (2220) coupling the second data width of the second processor (2224) to the first data width. The bus interface circuit (2220) further has bus master and bus slave circuitry coupled between the second processor (2224) and the arbiter circuit (2230). The bus bridge (2236), the bus interface (2220) and the first terminals and the DRAM memory controller (2250) have datapaths selectively interconnected in response to the arbiter circuit (2230). Other devices, systems and methods are also disclosed.

Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array

Abstract: A structured logic array is divided into hierarchical levels At a highest level (the chip level), blocks are interconnected by a system of chip busses A block interface couples each block to the chip bus system to allow the blocks to communicate with each other At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system At a lowest level, each sector includes a plurality of logic elements The logic elements are interconnected by a sector bus system The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system

Ring bus structure and it's use in flash memory systems

Abstract: A system and integrated circuit chips used in the system utilize a bus in the form of a ring to interconnect nodes of individual components for transfer of data and commands therebetween. An example system described is a memory having one or more re-programmable non-volatile memory cell arrays connected to each other and to a system controller by a ring bus.