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Balun

About: Balun is a research topic. Over the lifetime, 5375 publications have been published within this topic receiving 52256 citations. The topic is also known as: Telephone balance unit.


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Book
14 Mar 2012
TL;DR: In this article, the authors present an approach for the control of conducted emissions in an FFT-based EMI-based system, where the FFT is used to convert data from time to frequency.
Abstract: I. Fundamentals of Conducted Emission Design.- 1. Designing for EMC.- 1.1 Noise (EMI).- 1.2 EMI Source, Path, and Victim.- 1.3 Conductive Paths.- 1.4 Conduction or Radiation?.- 1.5 Design to Control Conducted Emissions.- 2. EMI Spectrum.- 2.1 Time and Frequency Domains.- 2.2 Description of FFT Software.- 2.3 Data Interpretation.- 2.4 Bare Bones FFT.- 2.5 Methods of Inputting Data to FFT.- 2.6 An Enhanced Version of FFT.- 2.7 Examples of FFT Conversions from Time to Frequency Domains.- 2.8 Some Possible Pitfalls.- 2.9 Subharmonics.- 3. Capacitor Modeling.- 3.1 The Capacitor Model.- 3.2 Parasitic Elements of Capacitors.- 3.3 Capacitor Types.- 3.4 Capacitor Voltage Ratings.- 4. Inductor Modeling.- 4.1 Inductor Losses.- 4.2 Inductor Capacitance.- 4.3 Air Core with Conductor Near Experiment.- 4.4 Inductor Cores Form Capacitive Paths.- 4.5 Inductor Impedance Curve.- 4.6 Parasitic Elements of Inductors.- 4.7 Simulation.- 5. Balun Modeling.- 5.1 Differential Mode Flux.- 5.2 Common Mode Flux.- 5.3 The Truth about Windings on Inductor Cores.- 5.4 Coupling K Factor.- 5.5 Differential Balun Inductance.- 5.6 Common Mode Balun Inductance.- 5.7 Effects of Load and Source Resistances on Attenuation.- 5.8 Balun Driving Impedance.- 5.9 Balanced Circuits.- 5.10 Design Criteria.- 5.11 Model.- 6. Filters.- 6.1 Parasitic Inductances and Capacitances.- 6.2 Academic LC Filter.- 6.3 Simple Real World LC Filter.- 6.4 Control Parasitics by Design.- 6.5 Parasitics Caused by Circuit Layout.- 6.6 Filter Circuit Design.- 6.7 Characteristic Impedance of LC Filters.- 6.8 Parallel Capacitors to Lower the ESR.- 6.9 LC Filter.- 6.10 Line Impedance Stabilization Networks.- 6.11 Filter Layout and Packaging Design.- 7. Grounding Electronic Circuits.- 7.1 Grounding.- 7.2 Safety Grounds.- 7.3 Ground Geometries.- 7.4 Ground Design for Packaging ElectronicCircuitry.- 7.5 Shielding.- 8. EMI Analysis.- 8.1 EMI Modeling.- 8.2 EMI Analysis Using SPICE.- II. Advanced Conducted Emission Design.- 9. EMC Regulations.- 9.1 FCC.- 9.2 VDE.- 9.3 MIL-STD-461.- 9.4 Voltage/LISN Measurement Method.- 9.5 Current/Capacitor Measurement Method.- 9.6 A Comparison of Some of the RF Conducted Emissions Standards.- 10. Switch Mode Power Supplies.- 10.1 Typical Power Supply Block Diagram.- 10.2 Typical Switch Mode Power Supply EMI Problem Areas.- 10.3 EMI Simulation and Laboratory EMI Test Setup.- 10.4 SMPS EMI Design Example.- 10.5 Model the Problem.- 10.6 Simulation Problems.- 10.7 Back to Fundamental Model.- 10.8 Identify the Players.- 10.9 Other Types of EMI Modeling for SMPS.- 10.10 Conclusion.- 11. Transistor and Diode Packaging Problem for EMI.- 11.1 New Semiconductor Device Packages.- 11.2 Common Mode Shorting Screens.- 11.3 Typical System with Power Conversion.- 11.4 Common Mode Current Paths.- 11.5 Conducted Emissions Reduction by Choice of Package.- 12. Circuit Examples.- 12.1 Example 1.- 12.2 Example 2.- 12.3 Example 3 (FFT).- 13. Computers and Digital Logic Circuitry.- 13.1 Conducted Emissions Coupling Paths.- 13.2 Sequential Logic and Clocks.- 13.3 Example of Internal Conducted Emissions.- 13.4 What Is the Best Bypass Capacitor?.- 13.5 Power Entry Capacitor.- 14. What This Analysis Method Is Not.- 14.1 Diagnostics.- 14.2 Fields.- 14.3 Radiation.- 14.4 Characteristic Impedances of Common Pairs of Conductors.- 14.5 Shortcomings of EMI Test Simulation as Described Herein.- 15. Magnetic Saturation Modeling.- 15.1 The Polarization of Magnetic Domains.- 15.2 Device, Core, and Material Properties.- 15.3 Core Geometry Effects.- 15.4 Effects of Cores Made of Two Different Materials.- 15.5 Some Crucial Parameters to Model Saturation.- 15.6 Methods of Integrating Voltage.- 15.7 Dr. Lauritzen's Saturation Model.- 15.8 The Core Geometry and Material Porosity Region of the B-H Loop.- 15.9 Curve Fitting versus Parametric Models.- 15.10 Conclusion.- Appendix. BASIC FFT.

47 citations

Patent
30 Sep 2002
TL;DR: The triple balanced mixer as discussed by the authors is an example of a planar mixer that is formed from several layers of low temperature co-fired ceramic and has a top layer, a bottom layer and inner layers.
Abstract: A triple balanced mixer has a compact size and is readily assembled. The triple balanced mixer has a planar substrate that is formed from several layers of low temperature co-fired ceramic. The substrate has a top layer, a bottom layer and inner layers. Vias extend through the substrate. A local oscillator balun and RF balun are located on the inner layers. An intermediate frequency balun is mounted to the top layer. Diode rings are mounted on the top layer. The diode rings are electrically connected to the local oscillator balun, the RF balun and the intermediate frequency balun through the vias.

47 citations

Journal ArticleDOI
TL;DR: In this article, a 2 to 40 GHz broadband active balun using 0.13 mum CMOS technology is presented, which exhibits a measured small signal gain of 0 plusmn1, with the amplitude imbalances below 0.5 dB and the phase differences of 180 plusmn10deg from 2 to40 GHz.
Abstract: A 2 to 40 GHz broadband active balun using 0.13 mum CMOS technology is presented in this letter. Using two-stage differential amplified pairs, the active balun can achieve a wideband performance with the gain compensation technique. This active balun exhibits a measured small signal gain of 0 plusmn1, with the amplitude imbalances below 0.5 dB and the phase differences of 180 plusmn10deg from 2 to 40 GHz. The core active balun has a low power consumption of 40 mW, and a compact area of 0.8 mm x 0.7 mm. This proposed balun achieved the highest operation frequency, the widest bandwidth, and the smallest size among all the reported active baluns.

47 citations

Patent
22 Mar 1994
TL;DR: In this paper, an antenna (i06) for an electronic apparatus is located in a flip element (104) of the apparatus housing, and a transformer (108) having a winding (201) in the flip element and a winding in the housing couples electromagnetic energy across the hinge while impedance matching and performing a balun function.
Abstract: An antenna (i06) for an electronic apparatus is located in a flip element (104) of the apparatus housing. A transformer (108), having a winding (201) in the flip element (104) and a winding (301) in the housing couples electromagnetic energy across the hinge while impedance matching and performing a balun function.

47 citations

Patent
01 Aug 1996
TL;DR: In this article, the transformer can be constructed in a balun layout, an autotransformer layout, a layout with the secondary separated from the primary and rotated with respect to an axis of the primary, or a transformer in a toroidal layout.
Abstract: Various embodiments of on chip-transformers constructed in separate metal layers in an insulator that serves as a dielectric which is formed on a substrate such as a silicon substrate. Windings with currents flowing in a first direction are constructed in a first metal layer and windings with currents flowing a second direction are constructed in a second metal layer. Windings in the first metal layer are connected to windings in the second metal layer by connectors such as vias. The transformer can be constructed in a balun layout, an autotransformer layout, a layout with the secondary separated from the primary, a layout with the secondary separated the primary and rotated with respect to an axis of the primary, a layout in which the transformer is a two stage transformer and with the first stage constructed orthogonal to the second stage, or a transformer in which the windings are constructed in a toroidal layout.

47 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022242
2021130
2020280
2019327
2018310