Balun

About: Balun is a research topic. Over the lifetime, 5375 publications have been published within this topic receiving 52256 citations. The topic is also known as: Telephone balance unit.

Analysis and design of a high-performance planar Marchand balun

Abstract: This paper presents an enhanced Marchand balun that offers excellent amplitude and phase balance performance. The enhanced Marchand balun is designed using compensated coupled lines. It employs capacitive compensation, a renowned technique for compensating the unequal even- and odd-mode phase velocities encountered in parallel-coupled microstrips. Analysis carried out in this study has proven that the finite directivity of coupled lines significantly affects the balun performance. The proposed capacitively-compensated Marchand balun is demonstrated at 2.1 GHz and has offered excellent results.

A compact CMOS Marchand balun incorporating meandered multilayer edge-coupled transmission lines

Abstract: This work presents a compact CMOS Marchand balun design, which consists of the meandered two-conductor edge-coupled complementary-conducting-strip coupled-line (CCS CL). The CCS CL, which is fully compatible with the standard CMOS process, provides various structural parameters to synthesize the desired coupling coefficient for Marchand balun realization. The prototype, which is fabricated by the standard 0.18-µm 1P6M CMOS technology, reveals circuit size of 240.0 µm × 240.0 µm (without contact pads). The measured results, which are collected based on 50-Ω system, demonstrate excellent agreements with those of the simulations. The input return loss is less than −15.0 dB from 21.6 GHz to 33.1 GHz. The measured insertion losses between input and two output ports (S 21 and S 31 ) are 5.90 dB and 4.38 dB at 23.6 GHz, respectively. The phase difference between two output ports is 180° ± 10° from 15.5 GHz to 40.0 GHz.

220–250-GHz Phased-Array Circuits in 0.13- $\mu{\hbox {m}}$ SiGe BiCMOS Technology

Abstract: This paper describes the design of 220-250-GHz phased-array circuits in 0.13- μm BiCMOS technology. The design aspects of the active and passive devices that are used in the phased-array systems, such as balun, Wilkinson divider, and branch-line coupler, are presented in details. A millimeter-wave vector modulator is designed to support both amplitude and phase control for beam-forming applications. The designed circuits are integrated together to form a four-channel 220-250-GHz phased-array chip. Each channel exhibits 360° phase control with 18 dB of amplitude control. The entire chip draws 167 mA from a 3.3-V supply. The millimeter-wave phase shifting and the low-power consumption makes it ideal for highly integrated scalable beam-forming systems for both imaging, radiometry, and communication applications.

Coupled-Line Sensor With Marchand Balun as RF System for Dielectric Sample Detection

Abstract: A novel nondestructive method for effective permittivity measurement and detection of sample’s permittivity change in microwave frequency range has been proposed, utilizing a Marchand balun and a coupled-line sensor. The out-of-phase excited coupled-line section is used to obtain high sensitivity on the covering sample, which can be as narrow as the spacing between coupled strips. Formulas describing balanced to unbalanced impedance transformation of a Marchand balun have been provided, hence the proposed method requires only one-port measurement to determine effective permittivity in a wide frequency range. The proposed setup has been theoretically and experimentally investigated. The obtained measurement results proved the usefulness of the proposed approach for dielectric sample detection.

A 28-GHz SOI-CMOS Doherty Power Amplifier With a Compact Transformer-Based Output Combiner

Abstract: This article presents a series voltage-combining Doherty power amplifier (PA) achieving high output power ( $P_{\mathrm {out}}$ ) and high power-back-off (PBO) efficiency for 28-GHz fifth-generation (5G) applications. We introduce a new transformer-based series output combiner design method to achieve a true-Doherty load modulation that uses a compact footprint. The output stages of the main PA and the auxiliary PA (aux. PA) both use a differential three-stacked FET topology for high output power without posing a reliability issue. The intermediate-node matching is achieved by using a shunt inductor for voltage waveform alignment and efficiency improvement. A modified differential quadrature hybrid is proposed to achieve the desired quadrature power splitting function without the need for an input balun. For the proof of concept, the proposed PA is implemented in a 22-nm CMOS fully depleted silicon-on-insulator (FD-SOI) technology with a core area of 0.2 mm2. At 28 GHz, the measured saturated output power ( $P_{\mathrm {sat}}$ ), 1-dB output compression point (OP1dB), and peak power-added efficiency (PAE) are 22.5 dBm, 21.1 dBm, and 28.5%, respectively. State-of-the-art International Technology Roadmap for Semiconductors (ITRS) figure-of-merit (FOM) and power density are achieved. The measured PAE at 6-dB PBO is 22.1%, which results in an efficiency enhancement ratio of 1.56/3.12 with respect to an ideal class-B and class-A PA. The proposed PA can support 2.4-Gb/s 64-quadratic amplitude modulation (64-QAM) and 0.8-Gb/s 256-QAM signal with a competitive average PAE. Excellent device reliability is validated by operating the implemented PA under 3-dB gain compression point for 12 h with less than 0.06-dB $P_{\mathrm {out}}$ variation. The proposed Doherty PA with a compact footprint is suitable for the integration purpose of future 5G multiple-input multiple-output (MIMO) and phased-array applications.