Bandwidth (signal processing)

About: Bandwidth (signal processing) is a research topic. Over the lifetime, 48550 publications have been published within this topic receiving 600741 citations. The topic is also known as: Bandwidth (signal processing) & bandwidth.

Spread-Spectrum Multiple-Access Communications

Abstract: In a direct-sequence spread-spectrum multiple-access communications system several asynchronous signals simultaneously occupy the same channel. Each of the signals employs a signature sequence which is selected to have certain desirable correlation properties. For multiple-access communications the primary goal is to be able to separate the spread-spectrum signals at the receiver even though they occupy the same bandwidth at the same time. This problem is considered in the sections which follow for various forms of direct-sequence spread-spectrum modulation including binary phase-shift keying, quadriphase-shift keying, and minimum-shift keying. The emphasis is on the analysis of system performance rather than on the selection of signature sequences. Hence this material complements the recent paper of Sarwate and Pursley (1980) which examines in detail the problem of signature sequence selection.

On the capacity formula for multiple input-multiple output wireless channels: a geometric interpretation

Abstract: The capacity of multiple input, multiple output wireless channels is computed for Ricean channels The novelty is a geometrical (ray-tracing) interpretation of the MIMO channel capacity formula to find array geometries which greatly enhance channel capacity compared to SISO systems

A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB

Abstract: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is imple- mented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time mod- ulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive contin- uous-time ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The ADC achieves 76-dB SNR, 78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply. Index Terms—Analog-to-digital conversion, CMOS analog inte- grated circuits, continuous-time modulation, continuous-time filters, delta-sigma modulation, low-pass filter, low power design, low-voltage design, multibit internal quantization, sigma-delta modulation.

Narrow bandpass filters using dual-behavior resonators

Abstract: This paper reports on a new concept of narrow bandpass filters leading to perfectly controlled electrical responses within both the required operating bandwidth and adjacent undesired bands. A specific topology is considered for such a "global synthesis": in comparison with conventional filter performances, it provides significant improvements in terms of rejection control. The attenuated frequencies are each located apart from the bandpass frequencies and controlled by means of n transmission zeros introduced through original dual-behavior resonators (DBRs). These resonators are based on the association of different parallel open-ended stubs and allow the designer to independently control the in-band and out-of-band responses of the filter. A global synthesis approach is also discussed on a simplified architecture based on stepped impedance stubs, and the experimental results shown clearly validate the proposed concept. This simplification reduces the number of degrees of freedom when designing a DBR, and consequently the two transmission zeros become dependent.