Showing papers on "Banyan switch published in 1992"

Performance of a crosspoint buffered ATM switch fabric

Abstract: The authors present a queuing analysis and a simulation study of banyan switch fabrics based on 2*2 switching elements with crosspoint buffering. In particular, the results apply to the PHOENIX switching element based banyan fabrics. The results indicate that crosspoint buffering provides throughput approaching the offered load under uniform traffic conditions. The effect of bursty traffic on the performance of the switch is studied. It is shown that a speedup factor of three or more is required to achieve acceptable delay and packet loss probability. It is also shown that the amount of buffer space required per port increases linearly with the burst size for a desired packet loss performance. For a given burst size the packet loss rate decreases exponentially as the buffer size is increased. The impact of crosspoint buffering and shared buffering in the switching elements on the performance of the banyan fabric is analyzed. >

Performance analysis of nonblocking packet switch with input and output buffers

Abstract: The performance of nonblocking packet switches such as the knockout switch and Batcher banyan switch for high-speed communication networks can be improved as the switching capacity L per output increases; the switching capacity per output refers to the maximum number of packets transferred to an output during a slot. The N*N switch with L=N was shown to attain the best possible performance by M.J. Karol et al. (1987). Here a N*N nonblocking packet switch with input and output buffers is analyzed for an arbitrary number of L such that 1 >

A large scale ATM switching network with sort-banyan switch modules

Abstract: A large-scale broadband self-routing switching network based on the three-stage construction of sort-banyan switch modules is proposed. The switching network uses only one kind of module, preserves the cell sequencing of a service, and is robust for all patterns of load on the ports. A multistage three-phase algorithm is designed to control the delivery of cells. The switching network is input queued and delivers at most one cell in a cell time slot to each output port from one of the input ports requesting delivery to that output port. The maximum throughput of the switching network is shown to be 0.458, which is about 78% of that of a single-stage sort-banyan switching network. With a buffer size of 20 cells, one can achieve a 40% loading with almost no buffer overflow. Parallelism is easily achieved by having multiple switching planes. It is shown that, with four switching planes, the network is close to being output-queued. >

Performance modelling of a multi-buffered banyan switch under bursty traffic

Abstract: The authors present an analytical model of a buffered banyan asynchronous transfer mode (ATM) switch which allows complex switching elements, bursty traffic, and nonuniform destination distributions and permits the analysis of large-scale switches. The ATM switch is analyzed by decomposing it into individual switching elements. Each switching element is then analyzed numerically in isolation assuming that its arrival and service processes are known. The parameters of the arrival and service processes of the switching elements are obtained using an iterative scheme. The results obtained are approximate and validation tests have shown that they have good accuracy. Using this model, the cell loss, throughput, and the mean time to traverse the switch were obtained for different traffic parameters and buffer sizes within a switching element. >

Broadband packet switches based on dilated interconnection networks

Abstract: A theoretical foundation for the study of a broad spectrum of fast packet switching techniques is developed. Based on this framework, the authors investigate the complexity of various packet switch designs and demonstrate the advantage of dilation as a switch-design technique. For a given loss probability requirement, it is shown that for an N*N switch, the required number of switch elements for both the parallel-banyan network and the tandem-banyan network is of order N(log N)/sup 2/, whereas the complexity of a dilated-banyan network is of order N log N (log log N). In addition, it is shown that the parallel banyan networks in a Batcher-parallel-banyan network can be replaced by a dilated-banyan network without sacrificing the nonblocking property. >

The analysis of a phase-delayed optical two-state switch

Abstract: A novel optical waveguide phase-delayed two-state switch that consists of a pair of asynchronous waveguides is presented. The performance of the switch is analyzed in detail. The simple structure of the device may lead to an easy implementation in optical switching, optical interconnects, and sensor applications. >

Design of a folded banyan switching network with by-pass links using a distribution cell sequence control

Abstract: The asynchronous transfer mode (ATM) is considered to be important as a key technology in realizing a broadband ISDN that can handle diversified services in a unified way. The high-speed burst multiple transmission system using ATM is proposed. This paper considers the folded Banyan network with by-pass links which is proposed as a cross-connect switch to be applied to the cross-connect MUX of the high-speed burst multiple transmission system. A routing method that preserves the time sequence of cells also is proposed and its cell transfer performance is analyzed. The proposed routing method is realized by a distributed control. It is shown that the method can be applied at the same time preserving the features of the folded Banyan network with by-pass links, which are the unified modularity and the expansion without interruption. For the performance evaluation, a method of analysis is presented which improves the approximation of the traditional analysis of the cell loss rate.

Performance analysis of banyan shift ATM switch

Abstract: The authors introduce a new ATM switch architecture based on banyan interconnection networks. Its hardware is less complex than that of an output queueing switch. The reduction in the hardware complexity can be obtained without either losing the self-routing property or suffering from performance degradation under uniform and nonuniform traffic. The switch is constructed with shift network. It has an internal buffer that is interconnected in the banyan networks. The shift networks allow a cell to be sent to the correct output port. It needs only the destination address to route a cell regardless of the state of the switch. Although the switch becomes blocking, it retains the self-routing property and achieves the maximum throughput of 100% with only small additional delay. >