Showing papers on "Banyan switch published in 1997"

A 4 X 4 superconducting Batcher-Banyan switch

Abstract: The paper describes a Batcher sorter and a Banyan network which together form a nonblocking and self-routing switch. The Batcher sorter sorts input packets in the order of their address values. This sorting operation guarantees no blocking in the succeeding Banyan network and presents an efficient way to check contention. The Banyan network distributes contention-free packets to their final destinations. The Batcher and Banyan switches were designed by using a three-junction SQUID gate family driven by three-phase powering clocks. The Batcher sorter is composed of 2/spl times/2 Batcher switching elements. Each Batcher switching element sorts two input packets in the order of their address values. A 4/spl times/4 Batcher sorter with 2-b data width, which is composed of six 2/spl times/2 Batcher switching elements, was fabricated by an Nb tri-layer process. Its correct operation was confirmed. The Banyan network consists of 2/spl times/2 Banyan switching elements. A 2/spl times/2 Banyan switching element with 2-b data width was also fabricated. The correct operation was confirmed up to 4 GHz by using a test pattern generator integrated on-chip.

Discrete-Time Queuing Analysis of Dual-Plane ATM Switch with Synchronous Connection Control

Abstract: In this paper, we propose an ATM switch with the rate more than gigabits per second to cope with future broadband service environments. The basic idea is to separate the connection control flow from the data information flow inside the switch. The proposed switch has a dual-plane switch matrix with the synchronous control algorithm. The queuing behaviors of the proposed switch are shown by the discrete-time queuing analysis. Numerical analyses are taken both in the non-blocking crossbar switch and the banyan switch with internal blocking. Results show that a proposed dual-plane 16x16 switch would have the acceptable performance with maximum throughput of about 95 percent.

Tandem-crosspoint ATM: switch architecture and its cost-effective expansion

Abstract: This paper proposes a high-speed input and output buffering ATM switch, named the tandem-crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at all crosspoints. The TDXP switch architecture offers several advantages. First, the TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. These merits make it easy to implement a high-speed ATM switch. Numerical results show that the TDXP switch can effectively eliminate HOL blocking and achieve high throughput. In addition, we discuss how TDXP switches can be combined to form larger switches in a cost-effective way. We clarify the relative advantages of the crossbar switch configuration and the three-stage Clos switch configuration in achieving a specific throughput. Because the three-stage Clos switch configuration is not strictly non-blocking, we introduce a nearly non-blocking condition and evaluate switch throughput under the condition. The evaluation shows that crossbar switch configuration becomes more cost effective as the throughput of individual switch LSIs, which depends on device technologies, increases.

Ring switch for telecommunication apparatus

Abstract: The apparatus has a ring circuit conversion switch (1) and four switching branches each with a switch device (D6-D9). The switch has a first pair of connection nodes (3,5) and an alternative pair of connection nodes (2,4). The switch devices have parallel switched compensation branches (L10,C10,L11,C11), each for generation of a parallel resonance together with a closed switch element. The allocation of a compensation branch for a switch element is dependent on the switch state of the ring circuit conversion switch.

Architecture Design of an ATM Switch Based on a High Speed Network

Abstract: One of the key issues that must be fulfilled to realize BISDN, is to develop high speed and high capacity ATM packet switches. For this, many technical problems must be investigated, such as design of switch architecture, development of switch protocols, and evaluation of the switch performance. In this paper we will propose an ATM switch with a shared medium architecture. The medium is a high speed fiber optic network with reservation based access protocol. The switch uses a novel interconnection topology between the switch units to reduce the fiber optics network aggregate data rate for a high dimensionality switch. The resultant switch dimensionality estimate shows that with a switch unit network bus rate of 4 Gb/s, a fully connected broadband switch with 16384 I/O STS-3C lines (155.52 Mb/s port bandwidth) can be realized. Moreover, the architecture of the switch allows a modular growth, meets the need for heterogeneous and dynamically changing mix of traffic, and provides multi-point connection capability.