Showing papers on "Banyan switch published in 1998"
07 Oct 1998
TL;DR: In this article, the ALCATEL broadcast-and-select switch with AWG gratings has been evaluated with three optical packet switches, namely, the broadcast and select switch, the feed forward delay switch, and the feed back delay switch.
Abstract: Optical packet switches offer high speed, fine granularity, flexibility and transparency to data rate and format. There has been much work on the design of optical packet switches each having distinct advantages and disadvantages. Nevertheless, their common limitation is optical splitting loss, which is compensated by optical amplifiers, further degrading performance because of the induced amplifier noise. Hence, it is desirable to design an optical packet switch with a low optical splitting loss. This study has focused on the ALCATEL broadcast-and-select switch, which has significant optical splitting and combining losses for large switches. Arrayed-waveguide gratings (AWG) have been chosen to reduce the switch splitting loss replacing the demultiplexers and Semiconductor Optical Amplifier gates (SOA gates) in the ALCATEL switch. The switch still has the same functionality with an AWG which can be used as an interconnect, and has been demonstrated with insignificant crosstalk of approximately 30 dB. In this paper, three optical packet switches using AWGs are studied; the broadcast-and-select switch, the feed-forward delay switch and the feed-back delay switch. An additional novel feature is their use of wavelength division multiplexed inputs and outputs. Here, their optical performance is investigated with respect to bit error rate and power penalty, and compared with the ALCATEL broadcast-and-select switch using SOA gates.
14 citations
TL;DR: The key concept is that two-dimensional segmental input/output patterns, rather than the conventional one-dimensional ones, are employed, which ensures that the two channels in a switching pair are always located at adjacent positions, which leads to an efficient selection between the straight and the Banyan connection.
6 citations
12 Oct 1998
TL;DR: A novel ATM switch called parallel-tree Banyan switch fabric (PTBSF) that consists of parallel Banyans arranged in a tree topology that exhibited stable and excellent performance with respect to cell loss and switching delay for all studied conditions as required by ATM traffic sources.
Abstract: We present a novel ATM switch called parallel-tree Banyan switch fabric (PTBSF) that consists of parallel Banyans arranged in a tree topology. Packets enter at the topmost Banyan. Internal conflicts are eliminated by using a conflict free 3/spl times/4 switching element which distributes conflicting cells over different Banyans. Thus, cell loss may occur only at the lowest Banyan. Increasing the number of Banyans leads to noticeable decrease in the cell loss rate. The switch can be engineered to provide arbitrarily high throughput and low cell loss rate without the use of input buffering nor cell pre-processing. The performance of the switch is evaluated analytically under uniform traffic load and by simulation under a variety of ATM traffic loads. Compared to other proposed architectures, the switch exhibited stable and excellent performance with respect to cell loss and switching delay for all studied conditions as required by ATM traffic sources. The advantages of PTBF are modularity, regularity, self-routing, low processing over head, high throughput and robustness under a variety of ATM traffic conditions.
4 citations
07 Jun 1998
TL;DR: The analysis and simulation results show that the proposed switch can achieve a required cell loss probability using fewer stages than previously reported switches.
Abstract: In this paper, we propose a new high performance ATM switch architecture based on a high connectivity multipath multistage interconnection network called augmented composite banyan network (ACBN). The ACBN is created by adding a link to each switching element of the composite banyan network, which is a multipath network with at least two disjoint paths and was originally proposed in Seo and Feng (1995). The switch performance is studied under uniform and full load conditions. The analysis and simulation results show that the proposed switch can achieve a required cell loss probability using fewer stages than previously reported switches.
2 citations
21 Jan 1998
TL;DR: The multicast function, required in the ATM switching architectures, is applied to a Tandem-Banyan network and the internal blocking condition, characteristic of every banyan is analyzed and a new solution is proposed, according to the kind of conflict.
Abstract: The multicast function, required in the ATM switching architectures, is applied to a Tandem-Banyan network. The internal blocking condition, characteristic of every banyan is analyzed and a new solution is proposed, according to the kind of conflict. Also the delay in the overall network is analyzed and compared with similar designs.
2 citations
17 Mar 1998
2 citations
Patent•
19 Aug 1998
TL;DR: In this article, a Time-Space Switch is connected to a sub-multiplexer to produce through connections of different switch planes (8k, 64k) by simple demultiplexing operations.
Abstract: The switch consists of a conventional PCM Time-Space Switch connected to a sub-multiplexer. The output signals from the Time-Space Switch are output in a special intermediate format (Z), which permits the sub-multiplexer to produce through connections of different switch planes (8k, 64k) by simple demultiplexing operations. The switch information for the 8k plane is distributed to the Time-Space Switch and the sum-multiplexer.
DOI•
01 Jan 1998
TL;DR: The fat-banyan (FAB) architecture is proposed which employs gradual increase in dilation from the input stage to the output stage of the network, which has dramatic impact on the implementation and architectural scalability of the FAB switch.
Abstract: Much research effort has been directed into the design and performance analysis of ATM switches to date. However, less work has been done in efficiently utilizing the switch resources (e.g. buffers and links) to achieve the required performance. The current techniques for designing and evaluating ATM switches focus mainly on achieving a specified global cell loss probability within a given maximum cell delay. While useful and necessary to ensure that the switch can provide an acceptable QoS, this approach cannot effectively measure other important qualities of an ATM switch such as resource utilization and implementation complexity. Further, as the use of the Internet increases and new multimedia applications emerge there is need for substantial improvement in capacity on Internet backbone links. The need for ever increasing packet delivery bandwidth makes it inevitable that switches will have to scale to handle larger aggregate bandwidth (quiet possibly in terabit-per-second) range and more importantly to maintain QoS delivery. This thesis proposes a unifying framework for the design and analysis of large scale ATM switches based on enhanced banyan topologies. The banyan architecture has been chosen as the target architecture for developing the framework, since it is a logiV depth network and is optimal in the use of switching elements. However, the standard banyan network suffers from internal blocking. In order to overcome blocking in the banyan network we have proposed the fat-banyan (FAB) architecture which employs gradual increase in dilation from the input stage to the output stage of the network. Gradually incrementing dilation has dramatic impact on the implementation and architectural scalability of the FAB switch. Further, the FAB switch is highly optimized in the utilization of the internal bandwidth by appropriate setting of the dilation parameter per stage. The FAB switch can scale to the terabit-per-sec range with reasonable increase in chip count. Also, there is minimal interaction between the different streams (VCs/VPs) traversing the switch, thus minimizing any effect on the QoS of a stream from other streams. The performance of the FAB is analyzed by analytical methods and by extensive computer simulations. It should be noted that the technique of optimizing