Showing papers on "Banyan switch published in 2001"

Very low crosstalk 1×2 digital optical switch integrated with variable optical attenuators

Abstract: A novel digital thermo-optic switch based on a polymer waveguide has been demonstrated. The proposed switch consists of a conventional 1/spl times/2 digital optical switch and compact variable optical attenuators, with both elements integrated in series. The switches exhibit very low crosstalk values of -42 and -40 dB, and the switching power is /spl sim/170 mW at 1.5 /spl mu/m.

SFQ standard cell-based circuit design of an internal link speeded-up Batcher-Banyan packet switch

Abstract: We are developing a single-flux-quantum (SFQ) packet switch for over 1-Tb/s switching systems. Investigation of several switch topologies leads us to select the Batcher-Banyan packet switch because of its simplicity and regularity. The packet switch structure we propose consists of simple 2/spl times/2 unit switches each connected by speeded-up internal links. Numeric simulation showed that the speeded-up links greatly improved the throughput by resolving packet blocking, which is a major drawback of the Banyan switch. High throughput compatible to a crossbar switch was attained by using links whose speed was quadrupled. Moreover, the throughput did not decrease even though the number of input/output ports increased. Taking the speed of SFQ basic gates into account, the cycle time of the 2/spl times/2 unit switch reaches 25 ps, which is sufficient to achieve the 40-GHz operation. If unit switches are connected by quadrupled internal links, the Batcher-Banyan switch can accept the 10-Gb/s external input rate per channel. This indicates that the total throughput of a 128/spl times/128 switch exceeds 1 Tb/s. The unit switch was designed down to the SFQ gate level. To design a large SFQ circuit, we built several "standard" SFQ cells whose shape was square or rectangular with a unit width and height. Such shapes make it easier to place and connect a number of cells. We show some experimental results of testing SFQ standard cells and logic circuits.

Digital thermo-optic switch integrated with variable optical attenuators

Abstract: Disclosed is a thermo-optic (TO) switch that reduces the difficulty in the fabrication process and has an excellent optical crosstalk. In the TO switch, variable optical attenuators utilizing higher-order mode generators are integrated to the both output ports of a conventional 1×2 digital TO switch of Y-branch type waveguide which uses mode evolution effect. Even when the Y-branch angle gets bigger, the inventive TO switch can maintain an excellent crosstalk without raising the switching power. Since a large Y-branch angle can reduce the difficulty in fabrication process, the inventive TO switch will increase the production rate. 1×2 optical switch is an essential device in an optical signal processing system such as optical communications, optical switches and optical sensors.

Novel architecture of optical switch based on acousto-optic interaction for telecommunication networks

Abstract: We propose a novel synchronous switch for telecommunication networks at a 1.5 μm wavelength. This switch is based on the acousto-optic interaction. In this paper, we discuss about the switch's constraints to be applicable in a network, and present an acousto-optic cell architecture using planar phased array piezoelectric transducers.

Sorting networks with applications to hierarchical optical interconnects

Abstract: The Banyan network is shown to have a computationally unsuitable structure for finding maximum passable subpermutations, which is proved NP-complete. Using some non-blocking properties on the cube and reverse Banyan networks, a network topologically equivalent to the Batcher sorter, but functionally equivalent to the Batcher-Banyan network is derived for routing incomplete permutations. A log/sub 2/ N(2w-1) stage radix sorter for w-bit inputs, including duplicate inputs, that uses only log/sub 2/ N+1 bit address headers for routing through each 2 log/sub 2/ N stages is shown, which can be used in sort-MIN type packet switches. Space-time sorting networks based on these principles are derived, which can be used in hierarchical wavelength multiplexed optical networks.

A new 4x4 wide-sense nonblocking photonic switching network

Abstract: In this paper, new switch architecture is proposed for nonblocking photonic switching. This switch is a 4x4 space division multistage network using 2x2 optical switch elements, which may be directional couplers, fabricated on titanium diffused lithium niobate (Ti: LiNb03) substrates. The idea behind the architecture is presented and some properties of the switch are derived and analyzed. The performance of the switch is also discussed and compared with other well-known designs.

Architecture of a reconfigurable low power gigabit ATM switch

Abstract: Multistage switch interconnects like banyan switches are preferred in high speed networks for their cascadable structure and suitability for VLSI implementation. However most of these switch implementations are monolithic in nature and do not provide flexibility of dynamic re-routing of cells from active ports through idle ports. In this paper we take a critical look at a basic 8/spl times/8 benes switch from the perspective of identifying smaller blocks which can be pipelined in space and temporally multiplexed to exploit hardware reuse. A topological analysis of a 8/spl times/8 benes switch is carried out to identify mutually exclusive path sets that can be overlayed for hardware reuse. Based on this analysis we arrive at a basic building block called X-Structure, using which a 8/spl times/8 switch is constructed. The X-structure supports dynamic re-routing of cells and power down mode. A communication controller is designed using the the X-Structure based ATM switch at its core. A performance evaluation of the switch indicates a power saving of 66.66% due to hardware reuse, an 18.6% increase in hardware utilization and an aggregate throughput of 2.66 Gbps for a 8/spl times/8 switch.

Recovery of lost cells in banyan ATM switching networks using RS codes

Abstract: In order to cater for communications users' needs in terms of high speed, high bandwidth and error free reception, researchers have focused their attention towards B-ISDN/ATM in recent years. Since the major efficiency of ATM networks depends on the ATM switching, we have focused our attention towards high throughput in an ATM switch architecture. The banyan switch architecture is taken for our study. We have simulated an 8/spl times/8 banyan architecture with the proposed scheme of using RS coder and decoder. The performance of the proposed architecture in terms of cell loss and average delay versus the cell arrival rate is presented.

Banyan switched processor datapath

Abstract: A data-processing system comprises a register file, a routing unit, a Banyan switch, a switch control unit, a constant generator, and an arithmetic logic unit. The arithmetic logic unit comprises a bitwise function unit, pipeline register, and an accumulator. The Banyan switch may have an internal bitwidth of w and comprise N switching stages. N may equal log 2 (w) or log 4 (w). In the case of log 2 (w) stages, each switching stage has N/2 switching cells. The routing unit comprises a control logic that generates a control signal, and various logics that respectively operate on various bit groups of the control signal. The switch control unit comprises a shift constants generator, a pipeline flip-flop, and a switch tree. A data-processing method implemented by the above system is also disclosed.

Cell loss recovery in Banyan networks using RS codes under Self-Similar traffic

Abstract: In order to cater the needs of the users in the communication field in terms of high speed, high bandwidth, error free reception, researchers focused their attention towards BISDN/ATM in the recent years. Since the major efficiency of the ATM networks depends on the ATM switching, in this paper, we focused our attention towards high throughput of an ATM switch architecture. The Banyan switch architecture is taken for our study in this paper. We have simulated an 8 X 8 Banyan architecture with the proposed scheme of using RS coder and decoder. The Banyan architecture has been studied for its performance with Self-Similar traffic. The performance of the proposed architecture in terms of cell loss and average delay versus the cell arrival rate is presented.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A scalable and high capacity router on multi-dimension crossbar switch principle

Abstract: Eventhough conventional multistage switch architecture such as a Banyan switch can support a high speed capacity, but it still has a high latency and is not scalable. Moreover under non-uniform traffic, blocking occurs. Therefore, a new switch architecture based on multi-dimensional crossbar (MDXB) switch is introduced, as a better solution. The MDXB switch is an interconnection among crossbar switches into multi-dimension network. We also propose a new node configuration and routing algorithm used in the MDXB switch to achieve even lower packet loss rate. The simulation results shown that MDXB switch achieves much higher throughput under a non-uniform traffic pattern.