scispace - formally typeset
Search or ask a question

Showing papers on "Banyan switch published in 2011"


Journal ArticleDOI
TL;DR: This paper proposes a new concept, called quasi-output-buffered switch, a deterministic switch that achieves 100 percent throughput and delivers packets from the same flow in the FIFO order and shows that packet-pair switches have better delay performance than most load-balanced switches with comparable construction complexity.
Abstract: It is well known that output-buffered switches have better performance than other switch architectures. However, output buffered switches also suffer from the notorious scalability problem, and direct constructions of large output-buffered switches are difficult. In this paper, we study the problem of constructing scalable switches that have comparable performance (in the sense of 100 percent throughput and first-in first-out (FIFO) delivery of packets from the same flow) to output-buffered switches. For this, we propose a new concept, called quasi-output-buffered switch. Like an output-buffered switch, a quasi-output-buffered switch is a deterministic switch that achieves 100 percent throughput and delivers packets from the same flow in the FIFO order. Using the three stage Clos network, we show that one can recursively construct a larger quasi-output-buffered switch with a set of smaller quasi output-buffered switches. By recursively expanding the three-stage Clos network, we obtain a quasi-output-buffered switch with only 2 × 2 switches. Such a switch is called a packet-pair switch in this paper as it always transmits packets in pairs. By computer simulations, we show that packet-pair switches have better delay performance than most load-balanced switches with comparable construction complexity.

4 citations


Proceedings ArticleDOI
18 Sep 2011
TL;DR: InP-on-SOI switch for all-optical-packet-switching as mentioned in this paper has 300/1300psec on/off switching times, >30dB extinction-ratio and no measurable pattern dependence or switch related power penalties up to a bit rate of 40Gb/sec.
Abstract: First ever demonstration of an InP-on-SOI switch for all-optical-packet-switching The switch has 300/1300psec on/off switching times, >30dB extinction-ratio and no measurable pattern dependence or switch related power penalties up to a bit rate of 40Gb/sec

2 citations


Proceedings Article
22 May 2011
TL;DR: The results indicate that the algorithm is capable to maintain the wide-sense nonblocking property of the switch under this control algorithm for all possible switch configurations.
Abstract: -In this paper, a control algorithm is proposed for a 2x3 nonblocking photonic switch. The switch is a space division multistage network using 2x2 optical switching elements which can serve as basic element for larger size networks. The idea behind the proposed algorithm is presented. The wide-sense nonblocking property of the switch under this control algorithm is tested and discussed. The results indicate that the algorithm is capable to maintain the wide-sense nonblocking property for all possible switch configurations. Keywordsphotonic switch; multistage network; wide-sense nonblocking; control algorithm

1 citations


Journal ArticleDOI
TL;DR: In this paper, a four-port optical switch composed of Mach-Zehnder interferometer switches with silicon waveguides is proposed, which has three possible connection states among the four ports.
Abstract: We propose a novel four-port optical switch, which has three possible connection states among the four ports. The device consists of two cross-bar switches, which join with unique connections. We fabricate a four-port optical switch composed of Mach-Zehnder interferometer switches with silicon waveguides; the fabricated switch has a small footprint of 800 × 400 μm2. The three-way switching operation with extinction ratios of up to 30 dB and switching time of 40 μs is demonstrated at telecom wavelengths.

1 citations