Showing papers on "Banyan switch published in 2018"

16 × 16 Silicon Optical Switch Based on Dual-Ring-Assisted Mach–Zehnder Interferometers

Abstract: In this paper, we report a nanosecond 16 × 16 silicon electro-optic switch chip based on a Benes architecture. The switch adopts dual-ring-assisted Mach–Zehnder interferometers as the basic building blocks. In each switch element, both TiN microheaters and PIN diodes are integrated for ring resonance alignment and high-speed switching, respectively. A transfer-matrix-based theoretical model is established to analyze the switch performances. The 16 × 16 switch is characterized by measuring the optical transmission spectra and quadrature phase-shift keying (QPSK) data transmission through 16 representative optical paths. The insertion loss of the entire switch chip is 10.6 ± 1.7 dB and the crosstalk is less than −20.5 dB. The 32-Gb/s QPSK signal is successfully switched to different destination ports by reconfiguring the optical paths, verifying the signal integrity after switching.

A low-overhead multicast bufferless router with reconfigurable Banyan network

Abstract: In modern Multi-Processors System-on-Chip (MP-SoC), it is highly desirable to provide hardware support for efficient multicast traffic. Recently, bufferless router has become a promising solution for NoC due to its simplicity and low overhead. However, existing multicast bufferless routers utilize the serialized switch allocator to allocate both unicast and multicast packets based on the packet priority one by one, which makes the router have a long critical path and lowers the frequency of the router. In this paper, we propose a low-overhead multicast bufferless router with a reconfigurable Banyan network (called Banyan_PR, PR is short for packets replication). The Banyan switch of the router can be configured as four modes (straight, exchange, U-multicast and L-multicast) according to the type of the incoming packets. For the U-multicast and L-multicast configurations, the multicast packet can be replicated adaptively to reduce the multicast latency. Using a 4 x 4 Banyan network instead of the serialized switch allocator, the Banyan_PR router has shorter critical path length and less area overhead. Synthesis results under a 28nm technology show that the Banyan_PR router can achieve the frequency of 1GHz and save 65% less area and 89% less power consumption than the existing deflection-routing-based multicast bufferless router (called DRM_PR_all) with the serialized switch allocator. Simulation results illustrate that the Banyan_PR router achieves 25%, 28% and 19% less latency on average than that of the router without packets replication (called Banyan_noPR) and 39%, 42% and 35% less latency on average than that of the DRM_PR_all router under three synthetic traffic patterns respectively.