Topic
Banyan switch
About: Banyan switch is a research topic. Over the lifetime, 242 publications have been published within this topic receiving 3452 citations.
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01 May 1991
1 citations
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01 Oct 2002
TL;DR: In this article, a switch scheduler is configured to allocate internal paths within the switch among a plurality of source and destination port pairs to avoid such path blocking, and the scheduler may also append one or more address bits (440) to addresses identifying the destination ports so that data input to the first stage (410) travels along its allocated path.
Abstract: A switching system may include a banyan switch (400) having three stages (410-430) to lessen internal path blocking within the switch. A switch scheduler (130) may be configured to allocate internal paths within the switch among a plurality of source and destination port pairs to avoid such path blocking. The scheduler may also be configured to append one or more address bits (440) to addresses identifying the destination ports so that data input to the first stage (410) travels along its allocated path. The switch scheduler may contain a number of hardware processing elements (700) to rapidly perform the allocation of the internal paths.
1 citations
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1 citations
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03 Jan 2001TL;DR: A critical look at a basic 8/spl times/8 benes switch from the perspective of identifying smaller blocks which can be pipelined in space and temporally multiplexed to exploit hardware reuse.
Abstract: Multistage switch interconnects like banyan switches are preferred in high speed networks for their cascadable structure and suitability for VLSI implementation. However most of these switch implementations are monolithic in nature and do not provide flexibility of dynamic re-routing of cells from active ports through idle ports. In this paper we take a critical look at a basic 8/spl times/8 benes switch from the perspective of identifying smaller blocks which can be pipelined in space and temporally multiplexed to exploit hardware reuse. A topological analysis of a 8/spl times/8 benes switch is carried out to identify mutually exclusive path sets that can be overlayed for hardware reuse. Based on this analysis we arrive at a basic building block called X-Structure, using which a 8/spl times/8 switch is constructed. The X-structure supports dynamic re-routing of cells and power down mode. A communication controller is designed using the the X-Structure based ATM switch at its core. A performance evaluation of the switch indicates a power saving of 66.66% due to hardware reuse, an 18.6% increase in hardware utilization and an aggregate throughput of 2.66 Gbps for a 8/spl times/8 switch.
1 citations
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16 Nov 2015TL;DR: In this paper, an asymmetric-port-count DC switch that can simplify fiber connection arrangement in a large-scale optical switch is presented. But the design of the switch is not discussed.
Abstract: We introduce an asymmetric-port-count DC switch that can simplify fiber connection arrangement in a large-scale optical switch. A 24×4 DC switch is monolithically implemented with PLC technologies and its good performance is experimentally confirmed.
1 citations