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Barrel shifter

About: Barrel shifter is a research topic. Over the lifetime, 729 publications have been published within this topic receiving 7241 citations.


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Patent
29 Jun 1990
TL;DR: In this article, a variable-length decoder is disclosed in which a received variable-word-length encoded bit stream is input to a buffer and read out in parallel sequences equal in length to the maximum length codeword.
Abstract: A variable-length decoder is disclosed in which a received variable-word-length encoded bit stream is input to a buffer (102) and read out in parallel sequences equal in length to the maximum length codeword. These sequences are read into cascaded latches (105, 107). The cascaded sequences in both latches are input to a barrel shifter (109) which provides from its multi-bit input, a sliding decoding window to a table-lookup memory device (112). A control signal directly shifts the position of the decoding window of the barrel shifter as each codeword is detected. To detect each codeword, the initial bits in the decoding window are compared with the codeword entries in the table-lookup memory. When a codeword is detected, the corresponding stored codeword length is accumulated (120) with previously accumulated codeword lengths to produce the control signal which directly shifts the decoding window by the number of bits in the just decoded word. When all the bits in the first latch have been decoded, the next bit sequence in the buffer is input to the second latch while the previous bit sequence in the second latch is transferred to the first latch. The decoding window is then adjusted to the beginning of the next undecoded sequence.

127 citations

Patent
05 Oct 1987
TL;DR: In this article, a digital signal processing apparatus having a host processor interfaced to a plurality of signal processing coprocessors through dual port memory elements is disclosed, where low level instructions directed toward the mechanics of performing a specific signal processing algorithm are contained in microcode.
Abstract: A digital signal processing apparatus having a host processor interfaced to a plurality of signal processing coprocessors through dual port memory elements is disclosed. Coprocessors represent microcoded machines wherein low level instructions directed toward the mechanics of performing a specific signal processing algorithm are contained in microcode. Thus, the host processor programs coprocessors using higher level functional instructions. Each of the coprocessors has a multiply-accumulator, a barrel shifter, an address generator, a hardware loop counter, and a microsequencer.

126 citations

Journal ArticleDOI
TL;DR: The proposed level shifter circuit can convert low- voltage digital input signals into high-voltage digital output signals and achieves low-power operation because it dissipates operating current only when the input signal changes.
Abstract: This paper presents a level shifter circuit capable of handling extremely low-voltage inputs. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input and output logic levels. The proposed level shifter circuit can convert low-voltage digital input signals into high-voltage digital output signals. The circuit achieves low-power operation because it dissipates operating current only when the input signal changes. Measurement results demonstrated that the circuit can convert a 0.23-V input signal into a 3-V output signal. The power dissipation was 58 nW for a 0.4-V 10-kHz input pulse.

117 citations

Patent
10 Jul 1998
TL;DR: In this article, a digital camera has a sensor for sensing an image, a processor for modifying the sensed image in accordance with instructions input into the camera and an output for outputting the modified image where the processor includes a series of processing elements arranged around a central crossbar switch.
Abstract: A digital camera has a sensor for sensing an image, a processor for modifying the sensed image in accordance with instructions input into the camera and an output for outputting the modified image where the processor includes a series of processing elements arranged around a central crossbar switch. The processing elements include an Arithmetic Logic Unit (ALU) acting under the control of a writeable microcode store, an internal input and output FIFO for storing pixel data to be processed by the processing elements and the processor is interconnected to a read and write FIFO for reading and writing pixel data of images to the processor. Each of the processing elements can be arranged in a ring and each element is also separately connected to its nearest neighbors. The ALU receives a series of inputs interconnected via an internal crossbar switch to a series of core processing units within the ALU and includes a number of internal registers for the storage of temporary data. The core processing units can include at least one of a multiplier, an adder and a barrel shifter. The processing elements are further connected to a common data bus for the transfer of a pixel data to the processing elements and the data bus is interconnected to a data cache which acts as an intermediate cache between the processing elements and a memory store for storing the images.

116 citations

Patent
04 Nov 1997
TL;DR: In this article, three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an output block whose outputs are coupled to a barrel shifter unit.
Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter. The decompressed stream of triangle data may then be passed to a traditional rendering pipeline, where it can be processed in full floating point accuracy, and thereafter displayed or otherwise used.

112 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20218
20205
201911
20189
201712
201620