Showing papers on "Barrier layer published in 1992"

Evidence of the barrier layer in the surface layer of the tropics

Abstract: Comparisons between isothermal depth to the top of the thermocline, and the mixed layer depth based on a ot criterion were undertaken for the tropical world oceans. In three equatorial regions, a shallower mixed layer than isothermal layer occurs, implying the presence of a strong halocline above the thermocline. This distance separating the top of the thermocline and the bottom of the mixed layer is referred to as the "barrier layer", in relation to its impediment to vertical heat flux out of the base of the mixed layer. Different mechanisms are responsible for maintaining the barrier layer in each of the three regions. In the western equatorial Pacific Ocean a salinity budget confirmed that heavy local precipitation most likely results in the isothermal but salt-stratified layer. In the northwest equatorial Atlantic, it is hypothesized that high salinity waters are subducted at the subtropics during winter and advected westward as a salinity maximum in the upper layers of the tropics, resulting in the barrier layer. In the eastern equatorial Indian Ocean, monsoonal related rainfall and river runoff contribute significantly to the freshwater flux, producing salt stratification in the surface. These results suggest the need to include the effects of salinity stratification when determining mixed layer depth.

Dielectric confinement effect on excitons in Pbl 4 -based layered semiconductors

Abstract: Optical properties of excitons in conventional semiconductor quantum-well structures derive from the spatial confinement of electrons and holes by variations in the electronic potential across the barrier and the well layers. However, a barrier layer with a smaller dielectric constant can substantially increase the binding energy of excitons in the well, especially when the dielectric constant in the barrier layer is sizably smaller than that in the well layer (eb < ew). Theory suggests that the binding energy of excitons in the well can substantially exceed the value of four-exciton Rydbergs, the ideal limit of the conventional two-dimensional (2D) system.

Mechanism of isothermal oxidation of the intel-metallic TiAl and of TiAl alloys

Abstract: The oxidation behavior of Ti36Al, Ti35Al-0.1C, Ti35Al-1.4V-0.1C, and Ti35 Al-5Nb-0.1C (mass-%) in air and oxygen has been studied between 700 and 1000°C with the major emphasis at 900°C. Generally an oxide scale consisting of two layers, an outward- and an inward-growing layer, formed. The outward-growing part of the scale consisted mainly of TiO2 (rutile), while the inward-growing part is composed of a mixture of TiO2 and α-Al2O3. A barrier layer of Al2O3 on TiAl between the inner and the outer part of the scale was visible for up to 300 hr. Under certain conditions, the Al2O3 barrier dissolved and re-precipitated in the outer TiO2 layer. This “shift” leads to an effect similar to breakaway oxidation. Only the alloy containing Nb formed a longlasting, protective Al2O3 layer, which was established at the metal/scale interface after an incubation period of 80–100 hr. During this time, Nb was enriched in the subsurface zone up to approximately 20 w/o. The growth of the oxide scale on TiAl-V obeyed a parabolic law, because no Al2O3 barrier layer formed; large Al2O3 particles were part of the outward-growing layer. A brittle α2-Ti3Al-layer rich in O formed beneath the oxide scale as a result of preferential Al oxidation particularly when oxidized in oxygen. Oxidation in air can lead also to formation of nitrides beneath the oxide scale. The nitridation can vary between the formation of isolated nitride particles and of a metal/Ti2AlN/ TiN/oxide, scale-layer system. Under certain conditions, nitride-layer formation seemed to favor protective Al2O23 formation at the metal/scale interface, however, in general nitridation was detrimental with the consequence that oxidation was generally more rapid in air than in oxygen.

Method for forming interconnect structures for integrated circuits

Abstract: A method is provided for forming interconnect structures for ULSI integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the sidewalls and bottom of interconnect trenches defined in a dielectric layer, and a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench. Advantageously, the metal layer forming interconnect comprises a layer of copper which is deposited by chemical vapour deposition from an organo-metallic precursor at low temperature. Etching back and planarization of the barrier layer and the metal layer is accomplished by chemical mechanical polishing. Second and subsequent levels of metallization are provided by repeating the process steps, as required, to provide another dielectric layer defining interconnect trenches, selectively lining the trenches with a conformal barrier layer and then filling the trenches with selective deposition of a conformal conductive layer of metal, with planarization of the resulting conformal layers by chemical mechanical polishing. Preferably, via holes forming contacts to underlying device structures are filled with copper or tungsten.

Bilayer metallization cap for photolithography

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO₂. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

Method of filling contacts in semiconductor devices

Abstract: An improved method of filling vias and openings in semiconductor devices comprises first faceting the top of the openings, depositing in sequence a barrier layer, as of TiN, treating the barrier layer to reduce its porosity, depositing a titanium-containing wetting layer, sputter depositing a first layer of aluminum at low temperatures and sputter depositing a second layer of aluminum at high temperatures to fill the opening and planarize the layer. The improved method is carried out preferably in a multichamber sputtering system.

Method for the formation of tin barrier layer with preferential (111) crystallographic orientation

Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

Windproof and water resistant composite fabric with barrier layer

Abstract: A stretchable, drapable, windproof, water resistant and water vapor permeable composite fabric including an inner layer of fabric, a polyurethane barrier and an outer layer of fabric. The barrier is constructed to allow water vapor molecules to travel therethrough, but restricts the passage of wind and liquid water. The water vapor is transported to and travels through the barrier to the outer fabric layer where it is removed to the environment.

Metal chemical vapor deposition process using a shadow ring

Abstract: An improved process is disclosed for depositing a layer of metal on a semiconductor wafer wherein a shadow ring normally engages the end edge of the front surface of the wafer to inhibit deposition of the metal on the backside of the wafer and a barrier or nucleation layer is deposited on the unshielded portion of the front surface of the wafer prior to the deposition of the metal layer thereon, and wherein gases used to form the metal layer may contact and react with underlying materials on the front surface of the wafer beneath the shadow ring. The improvement in the process comprises depositing the barrier layer over the entire front surface of the wafer while the wafer and the shadow ring are spaced apart; and then depositing the metal layer on the front surface of the wafer, while engaging the shadow ring with the wafer to inhibit deposition on the backside of the wafer; whereby the deposition of the barrier layer over the entire front surface of the wafer will shield underlying materials on the front surface of the wafer beneath the shadow ring from reaction with one or more of the gases used in the deposition of the metal layer.

Method of producing oxide ceramic layers on barrier layer-forming metals and articles produced by the method

Abstract: A method of producing oxide ceramic layers on Al, Mg, Ti, Ta, Zr, Nb, Hf, Sb, W, Mo, V, Bi or their alloys by a plasma-chemical anodical oxidation in a chloride-free electrolytic bath having a pH value of 2 to 8 and a constant bath temperature of -30° to +15° C. A current density of at least 1 A/dm2 is maintained constant in the electrolytic bath until the voltage reaches a predetermined end value.

Capacitor having a ruthenate electrode and method of formation

Abstract: A capacitor (11) is formed overlying a dielectric layer (34). A conductive layer (36) is formed overlying the dielectric layer (34). An optional barrier layer (16) is formed to electrically connect and isolate the conductive layer (36) from a first electrode region (20) which has a ruthenate portion. A dielectric layer (22) is formed overlying the first ruthenate electrode region (20) to form a capacitor dielectric. A second electrode region (24) is formed overlying the dielectric layer (22). An optional barrier layer (28) is formed overlying the electrode region (24). A conductive layer (32) is formed overlying the optional barrier layer (28) and makes electric contact to the electrode region (24). A dielectric layer (30) is formed to electrically isolate the capacitor (11).

Engineering of ultrathin barriers in high TC, trilayer Josephson junctions

Abstract: Josephson junctions with ultrathin (25–40 A) barriers were fabricated using high TC, trilayer films grown by atomic layer‐by‐layer molecular beam epitaxy (ALL‐MBE). The films consisted of top and bottom electrodes of Bi2Sr2CaCu2O8, separated by a single molecular layer of a metastable compound, Bi2Sr2(Ca, Sr, Bi, Dy)n−1CunO2n+4, with n=5 to 11. Systematic variation of Bi or Dy doping on Ca sites in the barrier layer provided four orders of magnitude of tuning of both the junction critical current and the normal state resistance, while keeping their product approximately constant, near 0.5 mV. Barrier and junction engineering, on an atomic length scale, has been demonstrated for the first time.

Hermetically sealed packaged electronic system

Abstract: A hermetically sealed electronic package particularly adapted for high density interconnect (HDI) electronic systems, employs a ceramic substrate as the package base. The substrate is provided with module contact pads. A barrier support frame on the module contact pads divides them into inner and outer portions. A plurality of electronic components, such as integrated circuit chips, are fastened to the substrate within the perimeter of the barrier support frame, and interconnections are provided between inner portions of the module contact pads and contact pads on the electronic components. A polymer barrier layer is deposited over the area enclosed by the barrier support frame as well as a portion of the frame itself, and is overlaid with a metal barrier layer. A protective solder layer is deposited on the metal barrier layer to bridge any voids in the metal barrier layer.

Method for forming a titanium nitride barrier layer

Abstract: Two methods for substantially improving the integrity of a TiN barrier layer are disclosed. The first method allows an atmospheric anneal in a conventional semiconductor furnace. The atmospheric anneal substantially seals the exposed TiN surface preventing subsequent metal layers from migrating through the barrier layer. The second method involves a reaction within a plasma reactor using a plasma gas. The plasma gas reacts with titanium within the TiN film to form a desired titanium compound. The gas is adsorbed onto the TiN grains at the grain boundaries within the TiN film thus filling the grain boundaries and thus substantially preventing subsequent metal layers from migrating though the TiN barrier layer. The second method allows the deposition of TiN, the plasma reaction, and subsequent metal depositions to take place on the same equipment using the same evacuation cycle.

Low-temperature process metal-to-metal antifuse employing silicon link

Abstract: A metal-to-metal antifuse includes a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure. A barrier layer is disposed over the first metal layer. A first heavily-doped amorphous silicon layer is disposed over the barrier layer. A thin dielectric antifuse material is disposed over the first amorphous silicon layer. This dielectric can be nearly any dielectric such as nitride or oxide or a combination of these materials such as ONO and should have a breakdown voltage suitable for programming inside the integrated circuit. A second heavily-doped amorphous silicon layer is disposed over the dielectric layer. An upper electrode, comprising a second metal layer including an underlying barrier layer, is disposed over the second amorphous silicon layer. The first and second metal layers may comprise metal interconnect layers in the circuit structure.

Silicon substrate having YSZ epitaxial barrier layer and an epitaxial superconducting layer

Abstract: An HTSC material epitaxially deposited on a YSZ buffer layer on a surface of a monocrystalline silicon substrate has a zero resistance transition temperature of at least 85° K., a transition width (10-90%) of no more than 1.0° K., a resistivity at 300° K. of no more than 300 micro-ohms-centimeter and a resistivity ratio (at 300° K./100° K.) of 3.0± 0.2. The surface of the silicon substrate is cleaned using a spin-etch process to produce an atomically clean surface terminated with an atomic layer of an element such as hydrogen with does not react with silicon. The substrate can be moved to a deposition chamber without contamination. The hydrogen is evaporated in the chamber, and then YSZ is epitaxially deposited preferably by laser ablation. Thereafter, the HTSC material, such as YBCO, is epitaxially deposited preferably by laser ablation. The structure is then cooled in an atmosphere of oxygen.

Bonding method using solder composed of multiple alternating gold and tin layers

Abstract: A device such as a laser is bonded to a submount such as diamond by a process in which the submount is successively coated with an adhesion layer such as titanium, a barrier layer such as nickel, and a gold-tin solder-metallization composite layer formed by sequential deposition on the barrier layer a number (preferably greater than seven) of multiple alternating layers of gold and tin, the last layer being gold having a thickness that is equal to approximately one-half or less than the thickness of the (next-to-last) tin layer that it contacts immediately beneath it. The bonding is performed under applied heat that is sufficient to melt the solder-metallization composite layer. Prior to the bonding, (in addition to the submount) the device advantageously is coated with gold and optionally with a similar gold-tin solder-metallization composite layer, at least at locations where it comes in contact with the gold-tin solder-metallization composite layer.

Process for forming low resistance aluminum plug in via electrically connected to overlying patterned metal layer for integrated circuit structures

Abstract: A process is described for forming an aluminum plug in a via in an insulating layer in an integrated circuit structure by first depositing a layer of aluminum over the insulating layer in a multistep deposition which will also result in filling the via with aluminum to form an aluminum plug therein, followed by removal of any additional aluminum formed over the surface of the insulating layer, and subsequent formation of one or more patterned conductive layers over the insulating surface which is in electrical communication with the underlying aluminum plug in the via. The one or more patterned conductive layers formed over the insulating surface are characterized by superior electrical properties over the aluminum layer initially deposited and then removed. A barrier layer may be first formed over exposed portions of the underlying integrated circuit structure at the bottom of the via before it is filled with aluminum.

Oxygen and flavor barrier laminate including amorphous nylon

Abstract: A non-foil composite laminate for an improved container providing an effective barrier for the containment of essential oils and prevention of losses of vitamin C. The non-foil composite laminate comprises an inner barrier layer of amorphous nylon and outer layers of heat sealable olefin polymer, facilitating manufacture while retaining desirable barrier properties.

Cable having lightning protective sheath system

Abstract: A communications cable for use in buried environments in an outside plant includes a core comprising at least one transmission medium and a mechanically strengthened, thermal resistant barrier layer disposed about a plastic tubular member. A metallic shield and a plastic jacket are disposed about the barrier. The barrier layer may comprise a tape which is made of a material such as woven glass or an aramid fibrous material, for example, which is resistant to relatively high temperatures, which has suitable strength properties in all directions and at elevated temperatures and which is characterized by properties which cause the barrier layer to impede the passage therethrough of particles which are sufficiently large to cause damage to the core. In a preferred embodiment, the thermal barrier layer also includes provisions for preventing the longitudinal flow of water within the cable. Such a waterblocking capability may be provided by a barrier layer comprising a laminate comprising a high temperature resistant tapeand at least one other tape with a superabsorbent powder therebetween or anothertape which has been impregnated with a superabsorbent material.

Field effect transistor

Abstract: A field effect transistor in which a first compound semiconductor layer (2) functioning as a buffer layer, an InAs layer (3) functioning as an electron traveling layer, and a second compound semiconductor layer (4) functioning as an electron feeding layer or a barrier layer are formed in succession on a semiconductor substrate (1) having a different lattice constant from that of InAs. The first compound semiconductor layer (2) is in lattice matching with InAs substantially, and is formed of one selected from among AlGaAsSb, AlGaPSb, AlInAsSb or AlInPSb, whose band gaps are larger than that of InAs, and has a simple structure. On the substrate (1) having the different lattice constant from the InAs layer (3), a FET having excellent high-frequency characteristics can be realized.

CMOS device and process

Abstract: A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.

A plug contact with antifuse and method of manufacture thereof

Abstract: An antifuse particularly suitable for submicron geometries is presented. The antifuse is formed between a silicon layer (10), which could be a doped region of the semiconductor substrate, an epitaxial layer or a polysilicon layer, and an upper metal interconnection layer (19). In contact holes in a silicon dioxide layer insulating the silicon and metal interconnection layers from each other, the antifuses have a thick refractory metal layer (17) having a top surface approximately at the same level as the top surface of the insulating layer. Depending upon the process used to deposit the refractory metal layer, a thin adhesion layer may be located immediately below the refractory metal layer. Between the underlying silicon layer and upper interconnection layer, a thin semiconductor material layer of amorphous silicon (18) may be located either below the refractory metal layer or above it. At its bottom, the interconnection layer also has a barrier layer (18) to prevent any intermixing between the amorphous silicon layer and the metal interconnection layer.

Modified and robust self-aligning contact process

Abstract: The method is described for fabricating an integrated circuit having a combination of a capacitor and metal oxide semiconductor field effect transistor with gate electrodes and source/drain regions. The method features the use of silicon nitride or silicon oxynitride barrier layers. The barrier layer is a key to the successful lightly doped drain spacer etch process. The barrier layer aids in endpoint detection for the plasma etch. This allows for less loss of the field oxide and greater thickness control of the field oxide regions. Further, the silicon nitride endpoint detection allows for the removal of undesirable residual silicon oxide from the surface of the capacitor plate without loss of the polysilicon capacitor plate itself.

Method for forming a nitride layer using preheated ammonia

Abstract: A process for forming a titanium nitride barrier layer in semiconductor devices using preheated ammonia reduces susceptibility to junction spiking. In one form of the invention, a substrate having an overlying layer of titanium is heated to a predetermined temperature in a reaction chamber. An ammonia gas is preheated to temperature not less than 600°C and is introduced into the reaction chamber. The preheated ammonia gas and the titanium layer react to form a quality titanium nitride (TiN) layer which is highly resistant to the junction spiking phenomenon. Nitride layers of other Group IVB or Group VB elements of the periodic table may also be formed using the present invention.

Characterization of various aluminium oxide layers by means of spectroscopic ellipsometry

Abstract: This paper reports the characterization of both barrier type and porous type anodic oxide films on aluminium by means of spectroscopic ellipsometry (SE). In order to show the capabilities of the technique for quantitative determination of the layer characteristics, results based on ellipsometric data are correlated with complementary information from the analytical techniques transmission electron microscopy (TEM) and Auger electron spectroscopy (AES). It is concluded that ellipsometry yields an accurate characterization for the thicknesses and the interfacial properties of both the barrier layer and the porous layer. The porosity of the porous layer, determined with SE, is found to be in good agreement with the results obtained from TEM.

Twice-anodized aluminum article having an organo-phosphorus monolayer and process for making the article

Abstract: A twice-anodized aluminum substrate is anodized sequentially in first and second aqueous electrolytes. In the first, the substrate is conventionally anodized to produce (i) a porous anodic oxide layer having open pores and a passivation layer thereunder. The substrate, now singly-coated, is then anodized in the second electrolyte of an aqueous solution of an organophosphorus compound which generates a residue which is chemisorbed and covalently bonded to the substrate to form (ii) a monomolecular essentially continuous monolayer on the outer surface of (i), and at the same time, the second anodizing step produces (iii) a barrier layer of non-porous aluminum oxide under (i). The thickness of this barrier layer can be increased as a function of the voltage used while maintaining the thickness of (i) substantially constant, and (ii) protects (i) from dissolution. Depending upon the choice of the organophosphorus compound, a hydrophobic, or chemically resistant surface may be produced; or, a surface which provides a leaving group to be reacted with an appropriate organic coating to be applied after the triplex layer is formed.

Semiconductor laser element

Abstract: PURPOSE:To reduce threshold current by making a current flow parallel to an active layer in a semiconductor maser element having the active layer forming a lamination structure of a well layer being a light emitting layer and a barrier layer doped with impurities. CONSTITUTION:Firstly, by an MBE growth method, the following are grown in order on a semiinsulative GaAs substate 1; a GaAs buffer layer 2, an AlGaAs highly resistive barrier layer 3, an active layer 4, an AlGaAs highly resistive barrier layer 3, and a GaAs layer 5. After that, an N region 6 and a P region 7 are formed by diffusing impurities. Finally, an SiO2 film 9 and an electrode 8 are formed. Threshold currents were measured about a conventional semiconductor laser element and the above semiconductor laser element. In the case of the conventional semiconductor laser element wherein the current injection direction is vertical to an active layer 23, the threshold current was about 30mA. On the other hand, in the case of the above semiconductor laser element wherein the current injection direction is in parallel with the active layer 4, the threshold current was about 5mA, and remarkable reduction is confirmed.

Integrated circuit metallization with zero contact enclosure requirements and method of making the same

Abstract: A method for forming aluminum metallization for contacting a conductive element in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, a first aluminum alloy layer is formed within the contact, optionally with a barrier layer between it and the underlying electrode. An etch stop layer is formed thereover, of a material which has a low etch rate to an aluminum etchant species. A second, thicker, aluminum alloy layer is formed thereover. The second aluminum layer is etched until the etch stop layer is reached; the mask for defining the metal line may have an edge within the dimensions of the contact opening. After removal of the exposed etch stop layer, a timed etch removes the first aluminum alloy layer, without exposing the bottom of the contact. The metal line may thus be safely formed, without requiring an enclosure around the contact opening. According to an alternate embodiment, conductive or semiconductive sidewall spacers may be formed, upon which the metal etch can stop, leaving a metal line within the contact dimensions. A further alternative embodiment uses a conductive etch stop layer which covers the entire contact, and upon which the metal etch can stop within the contact opening.

Method of making metal oxide films having barrier properties

Abstract: A layer of silver metal or the like, included as one of a plurality of transparent coating layers upon a glass pane, is protected from staining by providing the pane with a barrier layer comprising the oxides of at least two metals of which one is Me(1) and another is Me(2) wherein Me(1) is titanium, zirconium or hafnium and Me(2) is zinc, tin, indium or bismuth. The barrier layer is non-transmissive of moisture and other staining agents, is amorphous and is free of grain boundaries.